公开(公告)号：US12021127B2

公开(公告)日：2024-06-25

申请号：US17508832

申请日：2021-10-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00 ,  H01L21/266

CPC classification number: H01L29/4236 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/7831 ,  H10B12/34 ,  H01L21/266 ,  H10B12/485 ,  H10B12/488

Abstract: The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a plurality of isolation regions in the substrate and an active region surrounded by the isolation regions. A p-type doped region is interposed between two n-type doped regions in the substrate. A buried gate structure is formed in the substrate and disposed between the p-type doped region and the n-type doped region. The buried gate structure comprises a gate conductive material, a gate insulating layer disposed over the gate conductive material and a gate liner surrounding the gate conductive material and the gate insulating layer. A plurality of contact plugs are formed on the p-type doped region and the plurality of n-type doped regions.

公开(公告)号：US11094692B2

公开(公告)日：2021-08-17

申请号：US16683229

申请日：2019-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L27/088 ,  H01L27/108 ,  H01L29/36 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8234

Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.

公开(公告)号：US11677008B2

公开(公告)日：2023-06-13

申请号：US17534799

申请日：2021-11-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L21/823456 ,  H01L27/088 ,  H10B12/34 ,  H10B12/488

Abstract: The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.

公开(公告)号：US11488964B2

公开(公告)日：2022-11-01

申请号：US17371119

申请日：2021-07-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L29/423 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

公开(公告)号：US11848353B2

公开(公告)日：2023-12-19

申请号：US17643404

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H10B12/00 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/76237 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851 ,  H10B12/053

Abstract: A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.

公开(公告)号：US11659707B2

公开(公告)日：2023-05-23

申请号：US17655791

申请日：2022-03-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/49 ,  H01L29/08 ,  H01L23/532 ,  H01L21/306

CPC classification number: H10B12/34 ,  H01L21/30604 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L29/0847 ,  H01L29/4925 ,  H01L29/4958 ,  H10B12/033 ,  H10B12/053 ,  H10B12/31 ,  H10B12/485 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.

公开(公告)号：US11101273B1

公开(公告)日：2021-08-24

申请号：US16799859

申请日：2020-02-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L27/108 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

公开(公告)号：US11502075B2

公开(公告)日：2022-11-15

申请号：US17357986

申请日：2021-06-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.

公开(公告)号：US11315930B2

公开(公告)日：2022-04-26

申请号：US16792157

申请日：2020-02-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/49 ,  H01L29/08 ,  H01L23/532 ,  H01L21/306

Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.

公开(公告)号：US10937886B2

公开(公告)日：2021-03-02

申请号：US16297747

申请日：2019-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.