公开(公告)号：US11935780B2

公开(公告)日：2024-03-19

申请号：US17454616

申请日：2021-11-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC: H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US10825898B2

公开(公告)日：2020-11-03

申请号：US16720796

申请日：2019-12-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.

公开(公告)号：US10242978B1

公开(公告)日：2019-03-26

申请号：US15794834

申请日：2017-10-26

Applicant: Nanya Technology Corporation

Inventor： Fang-Wen Liu ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L27/02 ,  H01L49/02

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

公开(公告)号：US11659707B2

公开(公告)日：2023-05-23

申请号：US17655791

申请日：2022-03-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/49 ,  H01L29/08 ,  H01L23/532 ,  H01L21/306

CPC classification number: H10B12/34 ,  H01L21/30604 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L29/0847 ,  H01L29/4925 ,  H01L29/4958 ,  H10B12/033 ,  H10B12/053 ,  H10B12/31 ,  H10B12/485 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.

公开(公告)号：US11101273B1

公开(公告)日：2021-08-24

申请号：US16799859

申请日：2020-02-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L27/108 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

公开(公告)号：US11488964B2

公开(公告)日：2022-11-01

申请号：US17371119

申请日：2021-07-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L29/423 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

公开(公告)号：US12107002B2

公开(公告)日：2024-10-01

申请号：US18484452

申请日：2023-10-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC: H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US11482419B2

公开(公告)日：2022-10-25

申请号：US17106626

申请日：2020-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

公开(公告)号：US10825931B2

公开(公告)日：2020-11-03

申请号：US15894954

申请日：2018-02-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L21/762 ,  H01L21/3065

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

公开(公告)号：US10818800B2

公开(公告)日：2020-10-27

申请号：US15894580

申请日：2018-02-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsien Hsieh ,  Tseng-Fu Lu ,  Jhen-Yu Tsai ,  Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.