公开(公告)号：US12107002B2

公开(公告)日：2024-10-01

申请号：US18484452

申请日：2023-10-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC分类号： H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC分类号： H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

摘要： A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US11895830B2

公开(公告)日：2024-02-06

申请号：US17541817

申请日：2021-12-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao

IPC分类号： H10B12/00 ,  H01L29/423 ,  H01L29/40 ,  H01L21/762

CPC分类号： H10B12/488 ,  H01L21/76224 ,  H01L29/401 ,  H01L29/4236 ,  H10B12/053

摘要： The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

公开(公告)号：US11688783B1

公开(公告)日：2023-06-27

申请号：US17544410

申请日：2021-12-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao

IPC分类号： H01L29/423 ,  H10B12/00

CPC分类号： H01L29/4236 ,  H10B12/34

摘要： The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

公开(公告)号：US12063771B2

公开(公告)日：2024-08-13

申请号：US17651068

申请日：2022-02-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu Lu ,  Chuan-Lin Hsiao

IPC分类号： H10B12/00 ,  H01L21/762 ,  H01L29/06

CPC分类号： H10B12/315 ,  H01L21/762 ,  H01L29/0649 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

摘要： A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.

公开(公告)号：US11935780B2

公开(公告)日：2024-03-19

申请号：US17454616

申请日：2021-11-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC分类号： H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC分类号： H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

摘要： A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US11832432B2

公开(公告)日：2023-11-28

申请号：US17552736

申请日：2021-12-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao

IPC分类号： H10B12/00

CPC分类号： H10B12/053 ,  H10B12/34

摘要： The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.