公开(公告)号：US11848298B2

公开(公告)日：2023-12-19

申请号：US17401863

申请日：2021-08-13

Applicant: Mitsubishi Electric Corporation

Inventor： Yosuke Nakata ,  Yuji Sato ,  Yoshinori Yokoyama

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/29084 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/85205 ,  H01L2924/37001

Abstract: A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other, the first conductor plate is exposed from the first principal surface, the second conductor plate is not exposed from the first principal surface, and the first and second conductor blocks are exposed from the second principal surface.

公开(公告)号：US10418295B2

公开(公告)日：2019-09-17

申请号：US16061019

申请日：2016-11-04

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshinori Yokoyama ,  Shinnosuke Soda ,  Narihito Ota ,  Kazuyasu Nishikawa ,  Akihisa Fukumoto

IPC: H01L23/13 ,  H01L23/12 ,  H01L23/373 ,  H01L23/36 ,  H01L23/40 ,  H01L23/00 ,  H01L29/739

Abstract: A power module includes an insulated circuit board, a semiconductor element, a first buffer plate, and first and second joining materials. The semiconductor element is disposed on a side of one main surface of the insulated circuit board. The first buffer plate is disposed between the insulated circuit board and the semiconductor element. The first joining material is divided into a plurality of portions in a plan view. The first buffer plate is higher in coefficient of linear expansion than the semiconductor element and lower in coefficient of linear expansion than the insulated circuit board. The first buffer plate is lower in Young's modulus than the semiconductor element.

公开(公告)号：US20140175615A1

公开(公告)日：2014-06-26

申请号：US14036009

申请日：2013-09-25

Applicant: Mitsubishi Electric Corporation

Inventor： Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Yoshinori Yokoyama ,  Shinnosuke Soda

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/291 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/0001

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的主表面上形成半导体元件; 在主表面和半导体元件上形成熔点为450℃以下的低熔点玻璃膜; 对基板进行热处理，同时用绝缘或半绝缘的加压夹具将低熔点玻璃膜压向基板的主表面，并烧结低熔点玻璃膜; 并在烧结低熔点玻璃膜之后将加压夹具留在低熔点玻璃膜上。

公开(公告)号：US11830795B2

公开(公告)日：2023-11-28

申请号：US17609424

申请日：2019-07-04

Applicant: Mitsubishi Electric Corporation

Inventor： Yuji Sato ,  Yoshinori Yokoyama ,  Motoru Yoshida ,  Jun Fujita

IPC: H01L23/498 ,  H01L23/053 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/053 ,  H01L24/48 ,  H01L2224/48245 ,  H01L2924/14252

Abstract: A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.

公开(公告)号：US11264318B2

公开(公告)日：2022-03-01

申请号：US16479747

申请日：2018-01-15

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshinori Yokoyama ,  Jun Fujita ,  Toshiaki Shinohara ,  Hiroshi Kobayashi

IPC: H01L23/52 ,  H01L23/31 ,  H01L23/36 ,  H01L23/433

Abstract: Provided is a semiconductor device free from chipping of a thin semiconductor element during transportation. The semiconductor device includes: a thin semiconductor element including a front-side electrode on the front side of the semiconductor element, and including a back-side electrode on the back side of the semiconductor element; a metallic member formed on at least one of the front-side electrode and the back-side electrode, the metallic member having a thickness equal to or greater than the thickness of the semiconductor element; and a resin member in contact with the lateral side of the metallic member and surrounding the periphery of the metallic member, with a part of the front side of the semiconductor element being exposed.

公开(公告)号：US10707146B2

公开(公告)日：2020-07-07

申请号：US16088532

申请日：2016-10-31

Applicant: Mitsubishi Electric Corporation

Inventor： Motoru Yoshida ,  Yoshiyuki Suehiro ,  Kazuyuki Sugahara ,  Yosuke Nakanishi ,  Yoshinori Yokoyama ,  Shinnosuke Soda ,  Komei Hayashi

IPC: H01L23/40 ,  H01L25/18 ,  H01L21/52 ,  H01L25/07 ,  H01L21/56 ,  H01L23/373

Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.

公开(公告)号：US09508564B2

公开(公告)日：2016-11-29

申请号：US14425142

申请日：2013-07-19

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshinori Yokoyama ,  Kazuyo Endo ,  Jun Fujita ,  Shinnosuke Soda ,  Kazuyasu Nishikawa ,  Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue

IPC: H01L21/00 ,  H01L21/52 ,  H01L23/10 ,  H01L21/50 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.

Abstract translation: 在基板上形成多个半导体元件。 在SOI衬底上形成有多个密封窗和支撑多个密封窗的支撑部。 通过使用加压构件将SOI衬底压靠在衬底上，并且SOI衬底的多个密封窗口通过布置在多个半导体元件周围的低熔点玻璃构件接合到衬底。 支撑部分与结合到基底的多个密封窗口分离。

公开(公告)号：US10727186B2

公开(公告)日：2020-07-28

申请号：US16315050

申请日：2017-07-06

Applicant: Mitsubishi Electric Corporation

Inventor： Shinnosuke Soda ,  Yoshinori Yokoyama ,  Hiroshi Kobayashi

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/373 ,  H01L21/52 ,  H01L25/07 ,  H01L23/48 ,  H01L25/18

Abstract: A power semiconductor device having a high degree of reliability even when an operable temperature of a power semiconductor element is sufficiently increased. The power semiconductor device includes: a power semiconductor element including an electrode formed on a first surface; a first stress mitigation portion connected to the electrode with a first bonding portion being interposed; and a wiring portion electrically connected to the first stress mitigation portion with a second bonding portion being interposed. A bonding strength of the first bonding portion is higher than a bonding strength of the second bonding portion.

公开(公告)号：US20150243530A1

公开(公告)日：2015-08-27

申请号：US14425142

申请日：2013-07-19

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshinori Yokoyama ,  Kazuyo Endo ,  Jun Fujita ,  Shinnosuke Soda ,  Kazuyasu Nishikawa ,  Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue

IPC: H01L21/52 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.

Abstract translation: 在基板上形成多个半导体元件。 在SOI衬底上形成有多个密封窗和支撑多个密封窗的支撑部。 通过使用加压构件将SOI衬底压靠在衬底上，并且SOI衬底的多个密封窗口通过布置在多个半导体元件周围的低熔点玻璃构件接合到衬底。 支撑部分与结合到基底的多个密封窗口分离。

公开(公告)号：US08816493B2

公开(公告)日：2014-08-26

申请号：US13921695

申请日：2013-06-19

Applicant: Mitsubishi Electric Corporation

Inventor： Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue ,  Yoshinori Yokoyama ,  Jun Fujita ,  Kazuyo Endo ,  Shinnosuke Soda ,  Kazuyasu Nishikawa

IPC: H01L23/12 ,  H01L29/78 ,  H01L23/00 ,  H01L23/60

CPC classification number: H01L23/564 ,  H01L23/04 ,  H01L23/06 ,  H01L23/10 ,  H01L23/60 ,  H01L23/66 ,  H01L29/78 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 Ω/□.

Abstract translation: 半导体器件包括：衬底; 衬底上的半导体元件; 在所述基板上的与所述半导体元件电连接的互连; 在所述基板上的窗框构件，围绕所述半导体元件并与所述互连件接触; 以及密封窗，其结合到所述窗框构件并封装所述半导体元件。 窗框构件是低熔点玻璃，并且具有106-1010＆OHgr / /□的薄层电阻。