公开(公告)号：US11114836B2

公开(公告)日：2021-09-07

申请号：US15094469

申请日：2016-04-08

Applicant: Mitsubishi Electric Corporation

Inventor： Rei Yoneyama ,  Fumitaka Tametani ,  Manabu Matsumoto ,  Haruhiko Takemoto ,  Hiroshi Yoshida ,  Motonobu Joko

IPC: H02H3/00 ,  H02H3/08 ,  H02H5/04 ,  H02M7/00 ,  H02H7/10 ,  H02H7/22 ,  H01L23/049 ,  H01L23/31 ,  H01L23/498 ,  H01L27/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/739 ,  H01L29/861 ,  H02H3/20 ,  H02M1/32 ,  H02M7/5387 ,  H02M1/08

Abstract: The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case.

公开(公告)号：US10790218B2

公开(公告)日：2020-09-29

申请号：US16404992

申请日：2019-05-07

Applicant: Mitsubishi Electric Corporation

Inventor： Hidetoshi Ishibashi ,  Hiroshi Yoshida ,  Daisuke Murata ,  Takuya Kitabayashi

IPC: H01L23/492 ,  H01L23/31 ,  H02M7/217 ,  H02M3/335 ,  H01L23/00

Abstract: A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.

公开(公告)号：US10770367B2

公开(公告)日：2020-09-08

申请号：US16159745

申请日：2018-10-15

Applicant: Mitsubishi Electric Corporation

Inventor： Takuya Kitabayashi ,  Hiroshi Yoshida ,  Hidetoshi Ishibashi ,  Daisuke Murata

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/12 ,  H01L23/58 ,  H01L23/492

Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.

公开(公告)号：US10204886B2

公开(公告)日：2019-02-12

申请号：US15766903

申请日：2016-01-29

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroshi Yoshida ,  Yuji Imoto ,  Hidetoshi Ishibashi ,  Daisuke Murata ,  Kenta Nakahara ,  Seiji Oka ,  Junji Fujino ,  Nobuhiro Asaji

IPC: H01L25/07 ,  H01L25/18 ,  H01L23/492 ,  C09D163/00 ,  B32B27/38

Abstract: A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.

公开(公告)号：US09755548B2

公开(公告)日：2017-09-05

申请号：US15130164

申请日：2016-04-15

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroshi Yoshida ,  Kyoko Oyama

IPC: H02M7/538 ,  H02M7/5387 ,  H03K17/06 ,  H03K17/691

CPC classification number: H02M7/5387 ,  H03K17/063 ,  H03K17/691 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

Abstract: A bootstrap compensation circuit includes: a plurality of resistors series-connected between a floating potential corresponding to a high-voltage-side potential and a reference potential; a second capacitor that has one end connected to a divided potential extraction point and has the other end connected to the reference potential, the divided potential extraction point located between the plurality of resistors; and an output circuit which supplies current to a first capacitor, according to a potential of the divided potential extraction point.

公开(公告)号：US10862479B2

公开(公告)日：2020-12-08

申请号：US16171770

申请日：2018-10-26

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroshi Yoshida

IPC: H03K17/56 ,  H03K19/0175 ,  H02M5/458 ,  H03K3/037 ,  H02M1/00

Abstract: A drive circuit includes: a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and a capacitor having one end connected to a high side main terminal of the switching device, wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops.

公开(公告)号：US09583407B2

公开(公告)日：2017-02-28

申请号：US14953953

申请日：2015-11-30

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroshi Yoshida ,  Yoshitaka Otsubo ,  Hidetoshi Ishibashi ,  Kenta Nakahara

IPC: H01L23/31 ,  H01L23/053 ,  H01L23/10 ,  H01L23/13 ,  H01L23/498 ,  H01L23/373 ,  H01L23/057 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/13 ,  H01L23/293 ,  H01L23/3142 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A first conductor layer is provided on a first surface of an insulating plate, and has a first volume. A second conductor layer is provided on a second surface of the insulating plate, and has a second volume. A third conductor layer is provided on a second surface of the insulating plate, and has a second volume. The third conductor layer has a mounting region thicker than the second conductor layer. The sum of the second and third volumes is greater than or equal to 70% and smaller than or equal to 130% of the first volume. A semiconductor chip is provided on the mounting region. A sealing part is formed of an insulator, and seals the semiconductor chip within a case.

Abstract translation: 第一导体层设置在绝缘板的第一表面上，并具有第一容积。 第二导体层设置在绝缘板的第二表面上，并具有第二体积。 第三导体层设置在绝缘板的第二表面上，并具有第二体积。 第三导体层具有比第二导体层厚的安装区域。 第二和第三体积的总和大于或等于第一体积的70％且小于或等于130％。 半导体芯片设置在安装区域上。 密封部由绝缘体形成，并将半导体芯片密封在壳体内。

公开(公告)号：US09443778B2

公开(公告)日：2016-09-13

申请号：US14717309

申请日：2015-05-20

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshitaka Otsubo ,  Hiroshi Yoshida ,  Junji Fujino ,  Masao Kikuchi ,  Junichi Murai

IPC: H01L21/52 ,  H01L23/053 ,  H01L23/498 ,  H01L23/31 ,  H01L23/32 ,  H01L23/29 ,  H01L21/48 ,  H01L21/54 ,  H01L23/40 ,  H01L23/00 ,  H01L23/13 ,  H01L23/373 ,  H01L23/24

CPC classification number: H01L23/29 ,  H01L21/486 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3178 ,  H01L23/32 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48139 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00

Abstract: It is possible to provide a semiconductor device which can be obtained at a high reliability by warping an insulating substrate stably into a convex shape while ensuring a close contact between a cooling member and the insulating substrate. The semiconductor device includes an insulating substrate, a semiconductor element disposed on a first surface of the insulating substrate, a case connected to the insulating substrate, and a resin filled inside the case. Assuming that the thickness of the insulating substrate is denoted by t1, the thickness of the resin is denoted by t2, the linear expansion coefficient of the insulating substrate is denoted by α1, and the linear expansion coefficient of the resin is denoted by α2, the relationship therebetween satisfies t2≧t1 and α2≧α1, and a second surface of the insulating substrate opposite to the first surface thereof is warped into a convex shape.

Abstract translation: 可以提供一种可以通过使绝缘基板稳定地翘曲成凸形而能够以高可靠性获得的半导体器件，同时确保冷却构件和绝缘基板之间的紧密接触。 半导体器件包括绝缘衬底，设置在绝缘衬底的第一表面上的半导体元件，连接到绝缘衬底的壳体和填充在壳体内的树脂。 假设绝缘基板的厚度为t1，树脂的厚度为t2，绝缘基板的线膨胀系数由α1表示，树脂的线膨胀系数由α2表示， 其关系满足t2≥t1和α2≥α1，并且与其第一表面相对的绝缘基板的第二表面弯曲成凸形。

公开(公告)号：US11777494B2

公开(公告)日：2023-10-03

申请号：US17743302

申请日：2022-05-12

Applicant: Mitsubishi Electric Corporation

Inventor： Yuta Tsukuma ,  Hiroshi Yoshida

IPC: H03K17/687 ,  H03K3/037

CPC classification number: H03K17/6871 ,  H03K3/037 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A level shift transistor of a first conductivity type configured to level shift a signal from a primary side circuit to a secondary side circuit between the primary side circuit having a primary side reference potential as reference and the secondary side circuit having a secondary side reference potential independent from the primary side reference potential as reference, a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit, a capacitor connected in parallel to the diode, and an inverter configured to invert the signal are provided. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, and a second main electrode thereof is connected to an output of the inverter. The inverter operates between the primary side reference potential and the primary side power supply.

公开(公告)号：US11270982B2

公开(公告)日：2022-03-08

申请号：US16473100

申请日：2017-01-30

Applicant: Mitsubishi Electric Corporation

Inventor： Norikazu Sakai ,  Hiroshi Yoshida ,  Hidetoshi Ishibashi ,  Nobuhiro Asaji

IPC: H01L25/07 ,  H01L21/48 ,  H01L23/492 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A metal mask is disposed on a copper base plate. A solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste on each of copper plates of the copper base plate. A semiconductor element and a conductive component are placed on the respective patterns of the solder pastes. A metal mask is disposed on the copper base plate. Then, a solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste covering each of the semiconductor element and the conductive component. A large-capacity relay board is disposed so as to come into contact with a corresponding pattern of the solder paste. A power semiconductor device is completed by performing heat treatment under a temperature condition of 200° C. or higher.