公开(公告)号：US10593758B2

公开(公告)日：2020-03-17

申请号：US15961322

申请日：2018-04-24

申请人： Magnachip Semiconductor, Ltd.

发明人： Seong Jo Hong ,  Soo Chang Kang ,  Ha Yong Yang ,  Young Ho Seo

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/266 ,  H01L29/66 ,  H01L29/10

摘要： A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

公开(公告)号：US10686051B2

公开(公告)日：2020-06-16

申请号：US16106622

申请日：2018-08-21

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jeong Hwan Park ,  Seung Sik Park ,  Ha Yong Yang

IPC分类号： H01L29/36 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/304 ,  H01L21/02 ,  H01L29/45 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

摘要： A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

公开(公告)号：US09691844B2

公开(公告)日：2017-06-27

申请号：US14939119

申请日：2015-11-12

申请人： Magnachip Semiconductor, Ltd.

发明人： In Su Kim ,  Jeong Hwan Park ,  Seung Sik Park ,  Ha Yong Yang

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/423 ,  H01L23/528 ,  H01L29/40 ,  H01L29/36 ,  H01L29/10

CPC分类号： H01L29/0619 ,  H01L23/528 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397

摘要： The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

公开(公告)号：US10263123B2

公开(公告)日：2019-04-16

申请号：US14734156

申请日：2015-06-09

申请人： Magnachip Semiconductor, Ltd.

发明人： Ho Hyun Kim ,  Ha Yong Yang ,  Jeong Hwan Park

IPC分类号： H01L21/283 ,  H01L21/822 ,  H01L27/02 ,  H01L29/866 ,  H01L29/861 ,  H01L29/66 ,  H01L29/43 ,  H01L29/06

摘要： Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events.

公开(公告)号：US10103221B2

公开(公告)日：2018-10-16

申请号：US15598730

申请日：2017-05-18

申请人： Magnachip Semiconductor, Ltd.

发明人： In Su Kim ,  Jeong Hwan Park ,  Seung Sik Park ,  Ha Yong Yang

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/423 ,  H01L23/528 ,  H01L29/40 ,  H01L29/10

摘要： The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

公开(公告)号：US09123769B2

公开(公告)日：2015-09-01

申请号：US13915810

申请日：2013-06-12

申请人： Magnachip Semiconductor, Ltd.

发明人： Ho Hyun Kim ,  Seung Bae Hur ,  Seung Wook Song ,  Jeong Hwan Park ,  Ha Yong Yang ,  In Su Kim

IPC分类号： H01L29/66 ,  H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397

摘要： Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.

摘要翻译： 提供了功率半导体器件及其制造方法。 功率半导体器件包括：第一外延层; 集电极层，形成在所述第一外延层的一侧上; 以及形成在所述第一外延层的另一侧上的第二外延层，所述第一外延层具有比所述第二外延层更高的掺杂浓度。

公开(公告)号：US11038019B2

公开(公告)日：2021-06-15

申请号：US16738044

申请日：2020-01-09

申请人： Magnachip Semiconductor, Ltd.

发明人： Seong Jo Hong ,  Soo Chang Kang ,  Ha Yong Yang ,  Young Ho Seo

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/266 ,  H01L29/66 ,  H01L29/10

摘要： A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

公开(公告)号：US10217836B2

公开(公告)日：2019-02-26

申请号：US15686874

申请日：2017-08-25

申请人： Magnachip Semiconductor, Ltd.

发明人： Jeong Hwan Park ,  Seung Sik Park ,  Ha Yong Yang

IPC分类号： H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/36 ,  H01L21/304 ,  H01L21/02 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423

摘要： A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.