公开(公告)号：US12021031B2

公开(公告)日：2024-06-25

申请号：US17098659

申请日：2020-11-16

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

公开(公告)号：US11862578B2

公开(公告)日：2024-01-02

申请号：US17575789

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/49822 ,  H01L25/165

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.

公开(公告)号：US11222850B2

公开(公告)日：2022-01-11

申请号：US16846381

申请日：2020-04-12

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

公开(公告)号：US11670596B2

公开(公告)日：2023-06-06

申请号：US17208175

申请日：2021-03-22

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Wen-Sung Hsu ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L24/20 ,  H01L24/73 ,  H01L2224/224 ,  H01L2224/73104

Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.

公开(公告)号：US20230060065A1

公开(公告)日：2023-02-23

申请号：US17872005

申请日：2022-07-25

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  Tsai-Ming Lai ,  Wei-Chen Chang

IPC: H01L23/043 ,  H01L23/06 ,  H01L23/00

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The two-part lid comprises an annular lid base and a cover plate removably installed on the annular lid base.

公开(公告)号：US20230044797A1

公开(公告)日：2023-02-09

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US11342267B2

公开(公告)日：2022-05-24

申请号：US16661219

申请日：2019-10-23

Applicant: MEDIATEK INC.

Inventor： Po-Hao Chang ,  Yi-Jou Lin ,  Hung-Chuan Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.

公开(公告)号：US20240055358A1

公开(公告)日：2024-02-15

申请号：US18383466

申请日：2023-10-24

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.

公开(公告)号：US11830820B2

公开(公告)日：2023-11-28

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

公开(公告)号：US20230005808A1

公开(公告)日：2023-01-05

申请号：US17901849

申请日：2022-09-01

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.