公开(公告)号：US20240242016A1

公开(公告)日：2024-07-18

申请号：US18395633

申请日：2023-12-25

Applicant: MEDIATEK INC.

Inventor： Chih-Jung Hsu ,  Chen Lien ,  Deng-Yao Tu ,  Po-Yang Chen ,  Guan-Qi Fang ,  Shu-Huan Chang ,  Yi-Hung Chen ,  Yao-Chun Su ,  Yu-Yang Chen

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/02

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F2119/02

Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.

公开(公告)号：US11222850B2

公开(公告)日：2022-01-11

申请号：US16846381

申请日：2020-04-12

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

公开(公告)号：US20250005257A1

公开(公告)日：2025-01-02

申请号：US18739311

申请日：2024-06-10

Applicant: MEDIATEK INC.

Inventor： Shu-Huan Chang ,  Yi-Hung Chen ,  Chih-Jung Hsu ,  Chen Lien ,  Guan-Qi Fang ,  Deng-Yao Tu ,  Po-Yang Chen

IPC: G06F30/398 ,  G06F119/02

Abstract: A method for performing automatic layout defect checking (ALDC) control regarding circuit design, associated apparatus and an associated computer-readable medium are provided. The method applicable to a processing circuit may include: providing a web-based entry in an ALDC control system running on a processing circuit, for any user among multiple users to upload at least a layout file of a package substrate design of at least one package substrate to the ALDC control system, in order to obtain at least the layout file from a client electronic device through the web-based entry; utilizing at least one backend program module to check the layout file according to a plurality of predetermined layout defect checking rules to generate at least one checking result, and create a layout defect checking report of the package substrate design; and sending the layout defect checking report corresponding to the layout file to the client electronic device.

公开(公告)号：US20240055358A1

公开(公告)日：2024-02-15

申请号：US18383466

申请日：2023-10-24

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.

公开(公告)号：US11830820B2

公开(公告)日：2023-11-28

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

公开(公告)号：US20220108954A1

公开(公告)日：2022-04-07

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.