公开(公告)号：US10037293B2

公开(公告)日：2018-07-31

申请号：US15015145

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: G06F13/38 ,  G06F13/362 ,  G06F13/40 ,  H04L7/00

CPC classification number: G06F13/362 ,  G06F13/4022 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/005

Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

公开(公告)号：US10104205B2

公开(公告)日：2018-10-16

申请号：US14925913

申请日：2015-10-28

Applicant: MediaTek Inc.

Inventor： Chun-Kai Huang ,  Yi-Hung Chen ,  Cheng-Ying Yu

IPC: H04L29/06

Abstract: Methods and apparatuses pertaining to flexible information mapping and modification of data packets are described. A method may involve receiving a data packet, modifying one or more attributes of the data packet, and outputting the modified data packet. In modifying the one or more attributes of the data packet, the method may involve extracting information from the data packet, the information including one or more user-defined fields (UDFs) in a header of the data packet. The method may also involve defining one or more source user-defined fields (SUDFs) according to at least one UDF of the one or more UDFs. The method may further involve performing one or more actions with respect to at least one SUDF of the one or more SUDFs.

公开(公告)号：US20160050299A1

公开(公告)日：2016-02-18

申请号：US14925913

申请日：2015-10-28

Applicant: MediaTek Inc.

Inventor： Chun-Kai Huang ,  Yi-Hung Chen ,  Cheng-Ying Yu

IPC: H04L29/06 ,  H04L12/861

CPC classification number: H04L69/22 ,  H04L69/08

Abstract: Methods and apparatuses pertaining to flexible information mapping and modification of data packets are described. A method may involve receiving a data packet, modifying one or more attributes of the data packet, and outputting the modified data packet. In modifying the one or more attributes of the data packet, the method may involve extracting information from the data packet, the information including one or more user-defined fields (UDFs) in a header of the data packet. The method may also involve defining one or more source user-defined fields (SUDFs) according to at least one UDF of the one or more UDFs. The method may further involve performing one or more actions with respect to at least one SUDF of the one or more SUDFs.

Abstract translation: 描述了关于数据分组的灵活信息映射和修改的方法和装置。 方法可以包括接收数据分组，修改数据分组的一个或多个属性，以及输出修改的数据分组。 在修改数据分组的一个或多个属性时，该方法可以涉及从数据分组提取信息，该信息包括数据分组头部中的一个或多个用户定义字段（UDF）。 该方法还可以包括根据一个或多个UDF的至少一个UDF定义一个或多个源用户定义字段（SUDF）。 该方法可以进一步涉及针对一个或多个SUDF的至少一个SUDF执行一个或多个动作。

公开(公告)号：US20160239444A1

公开(公告)日：2016-08-18

申请号：US15015145

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: G06F13/362 ,  G06F1/06 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4022 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/005

Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

Abstract translation: 晶片级封装具有第一裸片和第二裸片。 第一管芯具有布置成产生第一时钟的第一时钟源，被布置为产生发送数据的第一子系统，以及布置成根据第一时钟输出发送数据的输出电路。 第二管芯具有第二子系统，布置成产生第二时钟的第二时钟源和具有异步先进先出（FIFO）缓冲器的输入电路。 输入电路根据第一时钟对从异步FIFO缓冲器中的输出电路传送的发送数据进行缓冲，并根据第二时钟将异步FIFO缓冲器中缓存的发送数据输出到第二子系统。

公开(公告)号：US20250005257A1

公开(公告)日：2025-01-02

申请号：US18739311

申请日：2024-06-10

Applicant: MEDIATEK INC.

Inventor： Shu-Huan Chang ,  Yi-Hung Chen ,  Chih-Jung Hsu ,  Chen Lien ,  Guan-Qi Fang ,  Deng-Yao Tu ,  Po-Yang Chen

IPC: G06F30/398 ,  G06F119/02

Abstract: A method for performing automatic layout defect checking (ALDC) control regarding circuit design, associated apparatus and an associated computer-readable medium are provided. The method applicable to a processing circuit may include: providing a web-based entry in an ALDC control system running on a processing circuit, for any user among multiple users to upload at least a layout file of a package substrate design of at least one package substrate to the ALDC control system, in order to obtain at least the layout file from a client electronic device through the web-based entry; utilizing at least one backend program module to check the layout file according to a plurality of predetermined layout defect checking rules to generate at least one checking result, and create a layout defect checking report of the package substrate design; and sending the layout defect checking report corresponding to the layout file to the client electronic device.

公开(公告)号：US20160240497A1

公开(公告)日：2016-08-18

申请号：US15015110

申请日：2016-02-03

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

Abstract translation: 晶片级封装包括多个管芯和多个连接路径。 模具包括至少第一模具和第二模具。 模具并排布置，第一模具的第一侧与第二模具的第一侧相邻。 连接路径将布置在第一管芯的第一侧上的输入/输出（I / O）焊盘连接到布置在第二管芯的第一侧上的I / O焊盘，其中在第一管芯的第一侧上的相邻I / O焊盘 管芯通过仅在单个层上的连接路径连接到第二管芯的第一侧上的相邻I / O焊盘。 例如，第一模具与第二模具相同。 另一个例子，晶圆级封装是集成扇出（InFO）封装或衬底上晶片上的芯片（CoWoS）封装。 对于另一示例，将晶片级封装中的芯片组装起来以执行网络切换功能。

公开(公告)号：US20240242016A1

公开(公告)日：2024-07-18

申请号：US18395633

申请日：2023-12-25

Applicant: MEDIATEK INC.

Inventor： Chih-Jung Hsu ,  Chen Lien ,  Deng-Yao Tu ,  Po-Yang Chen ,  Guan-Qi Fang ,  Shu-Huan Chang ,  Yi-Hung Chen ,  Yao-Chun Su ,  Yu-Yang Chen

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/02

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F2119/02

Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.

公开(公告)号：US10515939B2

公开(公告)日：2019-12-24

申请号：US15015110

申请日：2016-02-03

Applicant: MEDIATEK INC.

Inventor： Yi-Hung Chen ,  Yuan-Chin Liu

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/538

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

公开(公告)号：US20150139235A1

公开(公告)日：2015-05-21

申请号：US14469607

申请日：2014-08-27

Applicant: MEDIATEK INC.

Inventor： Kuo-Cheng Lu ,  Yi-Hung Chen ,  Chang-Due Young

IPC: H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L49/25 ,  H04L49/354

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, a traffic manager, and a processor. The ingress packet processing circuit processes an ingress packet received from an ingress port to generate at least one parameter. The egress packet processing circuit has at least one programmable look-up table, refers to the at least one parameter to determine at least one action command set, and executes the at least one action command set for generating an egress packet to be forwarded through an egress port. The traffic manager is coupled between the ingress packet processing circuit and the egress packet processing circuit. The processor programs the at least one programmable look-up table. No action command in the at least one action command set is transmitted from the ingress packet processing circuit to the egress packet processing circuit through the traffic manager.

Abstract translation: 分组处理装置具有入口分组处理电路，出口分组处理电路，业务管理器和处理器。 入口分组处理电路处理从入口端口接收的入口分组以产生至少一个参数。 出口分组处理电路具有至少一个可编程查询表，参考至少一个参数来确定至少一个动作命令集，并且执行至少一个动作命令集，用于生成要通过 出口端口 流量管理器耦合在入口分组处理电路和出口分组处理电路之间。 处理器对至少一个可编程查询表进行编程。 至少一个动作命令集中的动作命令通过流量管理器从入口分组处理电路发送到出口分组处理电路。