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公开(公告)号:US11670596B2
公开(公告)日:2023-06-06
申请号:US17208175
申请日:2021-03-22
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Wen-Sung Hsu , I-Hsuan Peng , Yi-Jou Lin
IPC: H01L23/538 , H01L23/498 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/49816 , H01L24/20 , H01L24/73 , H01L2224/224 , H01L2224/73104
Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.
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公开(公告)号:US20230060065A1
公开(公告)日:2023-02-23
申请号:US17872005
申请日:2022-07-25
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Yi-Jou Lin , Tsai-Ming Lai , Wei-Chen Chang
IPC: H01L23/043 , H01L23/06 , H01L23/00
Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The two-part lid comprises an annular lid base and a cover plate removably installed on the annular lid base.
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公开(公告)号:US12021031B2
公开(公告)日:2024-06-25
申请号:US17098659
申请日:2020-11-16
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Yi-Jou Lin , I-Hsuan Peng , Wen-Sung Hsu
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L24/14
Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.
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公开(公告)号:US20230005808A1
公开(公告)日:2023-01-05
申请号:US17901849
申请日:2022-09-01
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Yi-Jou Lin , I-Hsuan Peng , Wen-Sung Hsu
IPC: H01L23/31 , H01L25/065 , H01L23/00 , H01L21/56
Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
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公开(公告)号:US20210111090A1
公开(公告)日:2021-04-15
申请号:US17035719
申请日:2020-09-29
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Yi-Jou Lin , I-Hsuan Peng , Wen-Sung Hsu
IPC: H01L23/31 , H01L25/065 , H01L21/56 , H01L23/00
Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
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公开(公告)号:US12136597B2
公开(公告)日:2024-11-05
申请号:US17515864
申请日:2021-11-01
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Nai-Wei Liu , Wen-Sung Hsu
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/065
Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.
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公开(公告)号:US11830851B2
公开(公告)日:2023-11-28
申请号:US17208198
申请日:2021-03-22
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Wen-Sung Hsu , I-Hsuan Peng , Yi-Jou Lin
IPC: H01L25/065 , H01L23/00 , H01L25/18 , H01L23/498
CPC classification number: H01L25/0657 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/18 , H01L23/49822 , H01L2224/13009 , H01L2224/13025 , H01L2224/13082 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/73253 , H01L2225/0652 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06548
Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
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公开(公告)号:US20210313271A1
公开(公告)日:2021-10-07
申请号:US17208175
申请日:2021-03-22
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Wen-Sung Hsu , I-Hsuan Peng , Yi-Jou Lin
IPC: H01L23/538 , H01L23/498 , H01L23/00
Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.
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公开(公告)号:US20240047427A1
公开(公告)日:2024-02-08
申请号:US18489814
申请日:2023-10-18
Applicant: MediaTek Inc.
Inventor: Yi-Lin Tsai , Wen-Sung Hsu , I-Hsuan Peng , Yi-Jou Lin
IPC: H01L25/065 , H01L23/00 , H01L25/18
CPC classification number: H01L25/0657 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/18 , H01L23/49822
Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
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公开(公告)号:US11854930B2
公开(公告)日:2023-12-26
申请号:US17901849
申请日:2022-09-01
Applicant: MEDIATEK INC.
Inventor: Yi-Lin Tsai , Yi-Jou Lin , I-Hsuan Peng , Wen-Sung Hsu
IPC: H01L23/48 , H01L23/31 , H01L25/065 , H01L23/00 , H01L21/56
CPC classification number: H01L23/3192 , H01L21/563 , H01L24/16 , H01L25/0655 , H01L2924/3511
Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
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