公开(公告)号：US20220238446A1

公开(公告)日：2022-07-28

申请号：US17718454

申请日：2022-04-12

Applicant: MediaTek Inc.

Inventor： Po-Hao CHANG ,  Yi-Jou Lin ,  Hung-Chuan Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.

公开(公告)号：US10932358B2

公开(公告)日：2021-02-23

申请号：US16114669

申请日：2018-08-28

Applicant: MEDIATEK INC.

Inventor： Duen-Yi Ho ,  Hung-Chuan Chen ,  Shang-Pin Chen

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  G06F13/40 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

公开(公告)号：US11342267B2

公开(公告)日：2022-05-24

申请号：US16661219

申请日：2019-10-23

Applicant: MEDIATEK INC.

Inventor： Po-Hao Chang ,  Yi-Jou Lin ,  Hung-Chuan Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.