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    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    1.
    发明公开
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240213194A1

    公开(公告)日：2024-06-27

    申请号：US18601003

    申请日：2024-03-11

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang JI

    IPC: H01L23/00

    CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05094 ,  H01L2224/13026

    Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220328433A1

    公开(公告)日：2022-10-13

    申请号：US17580699

    申请日：2022-01-21

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang JI

    IPC: H01L23/00

    Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive pad, a second insulation layer and a conductive trace. The first insulation layer is formed on the substrate and having a first through hole. The conductive pad is formed on the substrate through the first through hole. The second insulation layer has a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface. The conductive trace has a second surface and is connected to the conductive pad through the second through hole. The entire of the first surface is in the same level, and the entire of the second surface is in the same level.

    MOS DEVICE WITH ISOLATED DRAIN AND METHOD FOR FABRICATING THE SAME
    5.
    发明申请
    MOS DEVICE WITH ISOLATED DRAIN AND METHOD FOR FABRICATING THE SAME 有权
    具有隔离排水的MOS器件及其制造方法

    公开(公告)号：US20150091085A1

    公开(公告)日：2015-04-02

    申请号：US14039161

    申请日：2013-09-27

    Applicant: MediaTek Inc.

    Inventor： Puo-Yu CHIANG ,  Yan-Liang JI

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

    Abstract translation: 具有隔离漏极的MOS器件包括：具有第一导电类型的半导体衬底; 嵌入在半导体衬底的第一部分中的第一阱区，具有第二导电类型; 第二阱区，设置在所述半导体衬底的第二部分中，覆盖所述第一阱区并且具有所述第一导电类型; 设置在半导体衬底的第三部分中的第三阱区，覆盖具有第二导电类型的第一阱区; 第四阱区，设置在具有第一导电类型的第一和第三阱区之间的半导体衬底的第四部分中; 形成在半导体衬底上的栅叠层; 源区域，其设置在所述第二阱区域的具有所述第二导电类型的部分中; 以及设置在具有第二导电类型的第四阱区域的一部分中的漏极区域。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220384608A1

    公开(公告)日：2022-12-01

    申请号：US17735282

    申请日：2022-05-03

    Applicant: MEDIATEK INC.

    Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Ching-Han JAN

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423

    Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The semiconductor device also includes a gate spacer structure having a first spacer portion and a second spacer portion on opposite sidewalls of the gate structure. The semiconductor device also includes a source region and a drain region formed in the semiconductor substrate. The source region and a drain region are separated from the gate structure. The source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the gate spacer structure. The bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220328435A1

    公开(公告)日：2022-10-13

    申请号：US17687723

    申请日：2022-03-07

    Applicant: MEDIATEK Inc.

    Inventor： Yan-Liang JI

    IPC: H01L23/00

    Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive via and a conductive trace. The substrate includes a conductive component. The first insulation layer is formed on the substrate and having a first through hole exposing the conductive component. The conductive via is formed within the first through hole. The conductive trace is directly connected to the conductive via which is located directly above the first through hole.

    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION
    9.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION 审中-公开

    公开(公告)号：US20170263717A1

    公开(公告)日：2017-09-14

    申请号：US15425207

    申请日：2017-02-06

    Applicant: MEDIATEK INC.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/404 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831

    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220238712A1

    公开(公告)日：2022-07-28

    申请号：US17560496

    申请日：2021-12-23

    Applicant: MEDIATEK INC.

    Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Ching-Han JAN

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite the first sidewall. The semiconductor device also includes a gate spacer structure having two asymmetrical portions. One of the asymmetrical portions is formed on the first sidewall of the gate structure, and the other asymmetrical portion is formed on the second sidewall of the gate structure. The semiconductor device includes a source region and a drain region formed in the semiconductor substrate and aligned with the outer edges of the asymmetrical portions of the gate spacer structure. In some embodiments, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

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