公开(公告)号：US20160181418A1

公开(公告)日：2016-06-23

申请号：US14576301

申请日：2014-12-19

Applicant: MediaTek Inc.

Inventor： Chih-Chung CHIU ,  Puo-Yu CHIANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7835

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.

Abstract translation: 半导体器件包括形成在衬底中的具有第一深度的第一导电类型的阱区。 在阱区中形成第二导电类型的源极接触区域。 具有第二深度大于第一深度的50％的第二导电类型的漂移区形成在邻近阱区的衬底中。 在漂移区域中形成第二导电类型的漏极接触区域。 在源极接触区域和漏极接触区域之间的衬底上形成栅电极。 漏极接触区域与栅极间隔开，并且源极接触区域与栅电极相邻。 此外，还提供了一种制造半导体器件的方法。 该方法包括执行多步骤注入工艺以形成漂移区域。

公开(公告)号：US20150118816A1

公开(公告)日：2015-04-30

申请号：US14582626

申请日：2014-12-24

Applicant: MediaTek Inc

Inventor： Puo-Yu CHIANG ,  Yan-Liang JI

IPC: H01L29/66

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

Abstract translation: 一种制造金属氧化物半导体（MOS）器件的方法，执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层; 在由第一图案化掩模层曝光的半导体衬底的两个部分上执行第一离子注入工艺; 去除所述第一图案化掩模层并在所述半导体衬底上形成第二图案化掩模层，暴露所述第三阱区域的一部分; 对由第二图案化掩模层暴露的第三阱区的部分执行第二离子注入工艺; 对由第二图案化掩模层暴露的第三阱区的部分执行第三注入工艺; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

公开(公告)号：US20150091085A1

公开(公告)日：2015-04-02

申请号：US14039161

申请日：2013-09-27

Applicant: MediaTek Inc.

Inventor： Puo-Yu CHIANG ,  Yan-Liang JI

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

Abstract translation: 具有隔离漏极的MOS器件包括：具有第一导电类型的半导体衬底; 嵌入在半导体衬底的第一部分中的第一阱区，具有第二导电类型; 第二阱区，设置在所述半导体衬底的第二部分中，覆盖所述第一阱区并且具有所述第一导电类型; 设置在半导体衬底的第三部分中的第三阱区，覆盖具有第二导电类型的第一阱区; 第四阱区，设置在具有第一导电类型的第一和第三阱区之间的半导体衬底的第四部分中; 形成在半导体衬底上的栅叠层; 源区域，其设置在所述第二阱区域的具有所述第二导电类型的部分中; 以及设置在具有第二导电类型的第四阱区域的一部分中的漏极区域。