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    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION
    1.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION 审中-公开

    公开(公告)号：US20170263717A1

    公开(公告)日：2017-09-14

    申请号：US15425207

    申请日：2017-02-06

    Applicant: MEDIATEK INC.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/404 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831

    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

    MOS TRANSISTOR STRUCTURE WITH HUMP-FREE EFFECT
    2.
    发明申请
    MOS TRANSISTOR STRUCTURE WITH HUMP-FREE EFFECT 审中-公开
    具有无波纹效应的MOS晶体管结构

    公开(公告)号：US20170033214A1

    公开(公告)日：2017-02-02

    申请号：US15138683

    申请日：2016-04-26

    Applicant: MediaTek Inc.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/78

    Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.

    Abstract translation: 提供了MOS晶体管结构。 MOS晶体管结构包括具有包括第一边缘和与其相对的第二边缘的有源区域的半导体基板。 栅极层设置在半导体衬底的有源区上，并且具有延伸穿过有源区的第一和第二边缘的第一边缘。 具有第一导电类型的源极区域位于栅极层的第一边缘的一侧的有源区域和有源区域的第一和第二边缘之间。 第二导电类型的第一和第二重掺杂区分别位于与其第一和第二边缘相邻的有源区域中，并且彼此间隔开源区。

    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION
    3.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION 有权
    具有高电压运行功能的半导体器件

    公开(公告)号：US20160351705A1

    公开(公告)日：2016-12-01

    申请号：US15070289

    申请日：2016-03-15

    Applicant: MediaTek Inc.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66681

    Abstract: A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.

    Abstract translation: 半导体器件包括半导体衬底和形成在半导体衬底中的第一阱区。 绝缘体形成在第一阱区的一部分中和上方，并且在绝缘体的第一侧的第一阱区中形成第二阱区。 第一掺杂区形成在第二阱区中，并且第二掺杂区形成在与绝缘体的第一侧相对的第二侧的第一阱区中。 栅极结构形成在绝缘体上，第二阱区域和绝缘体之间的第一阱区域以及第二阱区域。 隔离元件形成在半导体衬底中，围绕第一阱区和第二阱区。 第一和第二掺杂区域从顶视图形成具有不对称构造。

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