公开(公告)号：US20220238712A1

公开(公告)日：2022-07-28

申请号：US17560496

申请日：2021-12-23

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Ching-Han JAN

IPC: H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite the first sidewall. The semiconductor device also includes a gate spacer structure having two asymmetrical portions. One of the asymmetrical portions is formed on the first sidewall of the gate structure, and the other asymmetrical portion is formed on the second sidewall of the gate structure. The semiconductor device includes a source region and a drain region formed in the semiconductor substrate and aligned with the outer edges of the asymmetrical portions of the gate spacer structure. In some embodiments, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

公开(公告)号：US20190131450A1

公开(公告)日：2019-05-02

申请号：US16225077

申请日：2018-12-19

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Chih-Wen HSIUNG

IPC: H01L29/78 ,  H01L49/02 ,  H01L27/06 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7817 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

公开(公告)号：US20240072044A1

公开(公告)日：2024-02-29

申请号：US18359123

申请日：2023-07-26

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Yan-Liang JI

IPC: H01L27/07 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0705 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.

公开(公告)号：US20230187144A1

公开(公告)日：2023-06-15

申请号：US18055128

申请日：2022-11-14

Applicant: MEDIATEK INC.

Inventor： Je-Min WEN ,  Cheng-Hua LIN ,  Ching-Han JAN

IPC: H01G4/38 ,  H01G4/01 ,  H01G4/018 ,  H01L49/02

CPC classification number: H01G4/38 ,  H01G4/01 ,  H01G4/018 ,  H01L28/60

Abstract: A capacitor structure includes a first comb-shaped electrode, a second comb-shaped electrode, a bottom electrode, an insulator layer, and a top electrode. The first comb-shaped electrode has a first pad and first fingers connecting to the first pad. The second comb-shaped electrode has a second pad and second fingers connecting to the first pad, wherein one of the second fingers is disposed between two adjacent first fingers. The bottom electrode includes a first portion, a second portion and a third portion which are spaced apart, wherein the first portion and the third portion are electrically coupled to the first comb-shaped electrode and the second comb-shaped electrode, respectively. The insulator layer is disposed over the bottom electrode. The top electrode is disposed over the insulator layer.

公开(公告)号：US20230038119A1

公开(公告)日：2023-02-09

申请号：US17811326

申请日：2022-07-08

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Ching-Han JAN

IPC: H01L49/02

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a polysilicon resistive structure, dummy polysilicon resistive structures, and a polysilicon ring structure. The semiconductor substrate has an active region and a passive region adjacent to the active region. The polysilicon resistive structure is disposed on an isolation structure in the passive region. The dummy polysilicon resistive structures are disposed on the isolation structure, respectively disposed outside opposite sides of the polysilicon resistive structure. The polysilicon ring structure is disposed on the isolation structure, encircling the polysilicon resistive structure and the dummy polysilicon resistive structures.

公开(公告)号：US20220384608A1

公开(公告)日：2022-12-01

申请号：US17735282

申请日：2022-05-03

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Ching-Han JAN

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The semiconductor device also includes a gate spacer structure having a first spacer portion and a second spacer portion on opposite sidewalls of the gate structure. The semiconductor device also includes a source region and a drain region formed in the semiconductor substrate. The source region and a drain region are separated from the gate structure. The source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the gate spacer structure. The bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.

公开(公告)号：US20170263764A1

公开(公告)日：2017-09-14

申请号：US15411099

申请日：2017-01-20

Applicant: MEDIATEK INC.

Inventor： Cheng-Hua LIN ,  Yan-Liang JI ,  Chih-Wen HSIUNG

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7817 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.