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    Multi-level flash memory cell capable of fast programming
    1.
    发明授权
    Multi-level flash memory cell capable of fast programming 有权
    能够快速编程的多级闪存单元

    公开(公告)号：US08466505B2

    公开(公告)日：2013-06-18

    申请号：US11077479

    申请日：2005-03-10

    申请人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

    发明人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

    摘要： A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

    摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括栅极结构，其包括在衬底上的隧道氧化物; 隧道氧化物上的浮动栅; 在浮动栅极上的电介质; 以及电介质上的控制栅极。 半导体器件还包括：沿着栅极结构的相对边缘的间隔物; 掺杂有与栅极结构的第一边缘横向间隔开的第一类型掺杂物的第一杂质区; 以及掺杂有与第一类型相反的第二类型掺杂剂的第二杂质区，漏极基本上在漏极间隔下方并且基本上与栅极结构的第二边缘对准。

    Multiple-gate transistors with reverse T-shaped fins
    3.
    发明授权
    Multiple-gate transistors with reverse T-shaped fins 有权
    具有反向T形翅片的多栅极晶体管

    公开(公告)号：US08455321B2

    公开(公告)日：2013-06-04

    申请号：US13294526

    申请日：2011-11-11

    申请人： Li-Shyue Lai ,  Jing-Cheng Lin

    发明人： Li-Shyue Lai ,  Jing-Cheng Lin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

    摘要： A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

    摘要翻译： 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

    Segmented MRAM memory array
    5.
    发明授权
    Segmented MRAM memory array 有权
    分段MRAM存储器阵列

    公开(公告)号：US07203129B2

    公开(公告)日：2007-04-10

    申请号：US10780171

    申请日：2004-02-16

    申请人： Wen-Chin Lin ,  Danny D. Tang ,  Li-Shyue Lai

    发明人： Wen-Chin Lin ,  Danny D. Tang ,  Li-Shyue Lai

    IPC分类号： G11C8/00

    CPC分类号： G11C11/16 ,  G11C2213/72 ,  G11C2213/74

    摘要： In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

    摘要翻译： 在一个示例中，MRAM存储器阵列包括多个字线，与字线交叉的多个位线，以及多个第一和第二二极管以及磁性隧道结存储器。 每个第一二极管包括阴极和耦合到每个位线的阳极。 每个第二二极管包括阳极和耦合到每个字线的阴极。 磁性隧道结存储器包括钉扎层，自由层和非磁性层。 非磁性层位于被钉扎层和自由层之间。 每个二极管位于位线和字线的交叉点处，并连接在相应交叉位线处的第一二极管和相应交叉字线处的第二二极管之间。

    MRAM cell with reduced write current
    6.
    发明授权
    MRAM cell with reduced write current 有权
    降低写入电流的MRAM单元

    公开(公告)号：US07170775B2

    公开(公告)日：2007-01-30

    申请号：US11030453

    申请日：2005-01-06

    申请人： Wen Chin Lin ,  Denny D. Tang ,  Li-Shyue Lai

    发明人： Wen Chin Lin ,  Denny D. Tang ,  Li-Shyue Lai

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C5/063

    摘要： A magnetic random access memory (MRAM) cell that includes an MRAM stack and a conductive line for carrying write current associated with the MRAM cell. The conductive line is oriented in a direction that is angularly offset from an easy axis of the MRAM stack by an acute angle, such as about 45 degrees.

    摘要翻译： 磁性随机存取存储器（MRAM）单元，其包括用于承载与MRAM单元相关联的写入电流的MRAM堆叠和导线。 导线沿着与MRAM堆叠的容易轴成角度偏移的方向定向为锐角，例如约45度。

    MRAM cell with reduced write current
    7.
    发明申请
    MRAM cell with reduced write current 有权
    降低写入电流的MRAM单元

    公开(公告)号：US20060146602A1

    公开(公告)日：2006-07-06

    申请号：US11030453

    申请日：2005-01-06

    申请人： Wen Lin ,  Denny Tang ,  Li-Shyue Lai

    发明人： Wen Lin ,  Denny Tang ,  Li-Shyue Lai

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC分类号： G11C11/16 ,  G11C5/063

    摘要： A magnetic random access memory (MRAM) cell including an MRAM stack and a conductive line for carrying write current associated with the MRAM cell in a direction that is angularly offset from an easy axis of the MRAM stack by an acute angle, such as about 45 degrees.

    摘要翻译： 磁性随机存取存储器（MRAM）单元，其包括MRAM堆叠和用于承载与MRAM单元相关联的写入电流的导线，所述写入电流以与MRAM堆叠的容易轴成角度偏移的方向（例如约45°） 度。

    Non-orthogonal write line structure in MRAM
    8.
    发明申请
    Non-orthogonal write line structure in MRAM 有权
    MRAM中的非正交写行结构

    公开(公告)号：US20050232005A1

    公开(公告)日：2005-10-20

    申请号：US10827079

    申请日：2004-04-19

    申请人： Wen Lin ,  Denny Tang ,  Li-Shyue Lai

    发明人： Wen Lin ,  Denny Tang ,  Li-Shyue Lai

    IPC分类号： G11C11/00 ,  G11C11/16

    CPC分类号： G11C11/16

    摘要： An MRAM cell including an MRAM cell stack located over a substrate and first and second write lines spanning at least one side of the MRAM cell stack and defining a projected region of intersection of the MRAM cell stack and the first and second write lines. The MRAM cell stack includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer interposing the pinned layer and the free layer. The first write line extends in a first direction within the projected region of intersection. The second write line extends in a second direction within the projected region of intersection. The first and second directions are angularly offset by an angle ranging between 45 and 90 degrees, exclusively. At least one write line may be perpendicular to the easy axis of free layer, while the other line may be rotated off the easy axis of the free layer by an angle which is larger than zero, such as to compensate for a shifting astroid curve.

    摘要翻译： MRAM单元包括位于衬底上的MRAM单元堆叠，以及横跨MRAM单元堆叠的至少一侧的第一和第二写入线，并且定义MRAM单元堆叠与第一和第二写入线之间的投影区域。 MRAM单元堆叠包括钉扎层，隧道势垒层和自由层，隧道势垒层插入被钉扎层和自由层。 第一写入线在投影的交叉区域内沿第一方向延伸。 第二写入线在投影的交叉区域内沿第二方向延伸。 第一和第二方向的角度偏移45度到90度之间的角度。 至少一条写入线可以垂直于自由层的容易轴，而另一条线可以从自由层的容易轴旋转大于零的角度，以补偿移动的星形曲线。

    Multiple-Gate Transistors with Reverse T-Shaped Fins
    10.
    发明申请
    Multiple-Gate Transistors with Reverse T-Shaped Fins 有权
    具有反向T形鳍的多栅极晶体管

    公开(公告)号：US20120058628A1

    公开(公告)日：2012-03-08

    申请号：US13294526

    申请日：2011-11-11

    申请人： Li-Shyue Lai ,  Jing-Cheng Lin

    发明人： Li-Shyue Lai ,  Jing-Cheng Lin

    IPC分类号： H01L21/20

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

    摘要： A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

    摘要翻译： 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。