公开(公告)号：US07561693B2

公开(公告)日：2009-07-14

申请号：US10621244

申请日：2003-07-15

申请人： Kyoung Ho Choi ,  Kil Ho Lee ,  Moon Seob Song ,  Joon Woo Lee

发明人： Kyoung Ho Choi ,  Kil Ho Lee ,  Moon Seob Song ,  Joon Woo Lee

IPC分类号： H04L9/00

CPC分类号： H04L63/104 ,  H04L1/16 ,  H04W12/02

摘要： Provided are a method for automatically entering into a secure communication mode that can perform secured voice communication between a transmission terminal and a reception terminal without changing or pre-setting a conventional wireless mobile communication system by forming part of a voice signal as a token for attempting secured voice communication, and a computer-readable recording medium for recording a program that implements the method. The method of the present research includes the steps of: a) generating a token based on a data having the lowest frequency of generation among the voice data outputted from a vocoder of the wireless communication terminal; b) at a transmission terminal receiving a request for a secure communication from a user and transmitting the token to a reception terminal; and c) at the transmission terminal entering into a secure communication mode based on an acknowledge token transmitted from the reception terminal, and performing secure communication with the reception terminal.

摘要翻译： 提供了一种用于自动进入安全通信模式的方法，该安全通信模式可以在传输终端和接收终端之间执行安全的语音通信，而不需要通过将语音信号的一部分形成为用于尝试的令牌来改变或预设常规的无线移动通信系统 安全的语音通信，以及用于记录实现该方法的程序的计算机可读记录介质。 本研究的方法包括以下步骤：a）基于从无线通信终端的声码器输出的语音数据中具有最低生成频率的数据生成令牌; b）在发送终端接收来自用户的安全通信的请求并将该令牌发送到接收终端; 以及c）在所述传输终端基于从所述接收终端发送的确认令牌进入安全通信模式，并且执行与所述接收终端的安全通信。

公开(公告)号：US5846887A

公开(公告)日：1998-12-08

申请号：US757161

申请日：1996-11-27

申请人： Kil Ho Lee ,  Byung Jin Cho

发明人： Kil Ho Lee ,  Byung Jin Cho

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/78 ,  H01L21/31

CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/2652 ,  H01L21/3221 ,  H01L29/7843

摘要： Disclosed is a method for the shallow junction having a low sheet resistance and an improved electric characteristics, using the medium temperature CVD oxide layer deposited on the source/drain regions into which impurity ions are implanted. The medium temperature CVD oxide layer, which has a compressive stress of 1.53.times.10.sup.9 dyne/cm.sup.2, causes the surface of the silicon substrate to be subject to tensile stress. By forming the medium temperature CVD oxide layer on the silicon substrate at a temperature of approximately 760.degree.-820.degree. C., the defects in the inside of the substrate move to the surface of the silicon substrate. As a result, the concentration of the defects in the inside of the silicon substrate decreases so that the small size extended defects are on the surface of the silicon substrate. These extended defects can be naturally removed from the surface of the silicon substrate by performing a follow-up process such as a metalization or an additional thermal treatment process.

摘要翻译： 公开了使用沉积在杂质离子注入的源极/漏极区域上的中等温度的CVD氧化物层，具有低的薄层电阻和改善的电特性的浅结的方法。 具有1.53×10 9达因/ cm 2的压缩应力的中温CVD氧化物层导致硅衬底的表面承受拉伸应力。 通过在硅衬底上在约760℃-820℃的温度下形成中温CVD氧化物层，衬底内部的缺陷移动到硅衬底的表面。 结果，硅衬底内部的缺陷的浓度降低，使得小尺寸延伸缺陷在硅衬底的表面上。 通过进行诸如金属化或附加的热处理工艺的后续工艺，可以从硅衬底的表面天然地除去这些延伸的缺陷。

公开(公告)号：US5773337A

公开(公告)日：1998-06-30

申请号：US929061

申请日：1997-09-15

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/31 ,  H01L21/265 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/2652 ,  H01L21/324 ,  H01L21/823418

摘要： There is disclosed a method for forming an ultra-shallow junction of a semiconductor device, comprising a four-stage RTA process following the ion implantation of dopants for source/drain junction, the RTA process being carried out with high temperature-elevating and -quenching rates between the stages, in such a way that relatively low temperatures are used for a short time in the first three stages in order to eliminate only the point defects, which greatly affect the diffusion of dopants, without diffusion of dopants while a relatively high temperature is taken in the last stage with the aim of allowing the dopants to diffuse a little to p.sup.+ and n.sup.+ shallow junctions, thereby obtaining an improvement in electrical activity and reducing junction current leakage and thus, improving the properties and reliability of the resulting semiconductor device.

摘要翻译： 公开了一种用于形成半导体器件的超浅结的方法，包括在用于源极/漏极结的掺杂剂的离子注入之后的四级RTA工艺，RTA工艺通过高温升温和淬火 阶段之间的速率，以这样的方式，在前三个阶段中相对较低的温度被使用短时间，以便仅消除极大地影响掺杂剂扩散的点缺陷，而不会使掺杂剂扩散，同时相对较高的温度 在最后阶段被采取，目的在于允许掺杂剂向p +和n +浅结点扩散一点，从而获得电活动的改善并减少结电流泄漏，从而提高所得半导体器件的性能和可靠性。

公开(公告)号：US5898007A

公开(公告)日：1999-04-27

申请号：US769751

申请日：1996-12-20

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/74 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/00 ,  H01L21/425

CPC分类号： H01L21/74 ,  H01L21/26513 ,  H01L21/823493

摘要： A method for forming wells of a semiconductor device which involves the formation of an additional ion implanted layer and a double rapid thermal annealing for a short period of time, thereby completely removing defects while maintaining a constant resistance in the silicon layer of the semiconductor device. The method includes the steps of providing a semiconductor substrate, sequentially implanting impurity ions in the semiconductor substrate four times, thereby sequentially forming an ion implanted layer adapted to form a well, an additional ion implanted layer, a channel stop ion implanted layer and an ion implanted layer adapted to control a threshold voltage in the semiconductor substrate, and conducting a rapid thermal annealing for the resulting structure for a short period of time in two steps.

摘要翻译： 一种用于形成半导体器件的阱的方法，其包括在短时间内形成额外的离子注入层和双重快速热退火，由此在半导体器件的硅层中保持恒定的电阻的同时完全去除缺陷。 该方法包括以下步骤：提供半导体衬底，在半导体衬底中顺序注入杂质离子四次，从而依次形成适于形成阱的离子注入层，附加离子注入层，通道停止离子注入层和离子 注入层，其适于控制半导体衬底中的阈值电压，并且在两个步骤中对所得结构进行短时间的快速热退火。

公开(公告)号：US06329237B1

公开(公告)日：2001-12-11

申请号：US09466896

申请日：1999-12-20

申请人： Kyong Min Kim ,  Chan Lim ,  Kil Ho Lee ,  Ki Seon Park

发明人： Kyong Min Kim ,  Chan Lim ,  Kil Ho Lee ,  Ki Seon Park

IPC分类号： H01L218242

CPC分类号： H01L21/31691 ,  C23C16/405 ,  C23C16/409 ,  C23C16/56 ,  H01L28/55

摘要： There is disclosed a method of making a high dielectric capacitor of a semiconductor device using Ta2O5, BST((Ba1−xSrx)TiO3) etc. of a high dielectric characteristic as a capacitor dielectric film in a very high integrated memory device. The present invention has its object to provide a method of manufacturing a high dielectric capacitor of a semiconductor device, which can effectively remove carbon contained within the thin film after deposition of the BST film and defects of oxygen depletion caused upon deposition of the thin film and which can also remove carbon contained within the thin film after deposition of the tantalum oxide film and defects of oxygen depletion caused upon deposition of the thin film, without further difficult processes or without any deterioration of the electrical characteristic of the capacitor. It employs the technology which is able to effectively removing defects of carbon and oxygen depletion within the thin film, by forming a plasma O3 gas having a good reactivity and by processing the plasma for the BST thin film and tantalum oxide film. Thus, it can extend the lifetime of the activated oxygen of oxygen, which had been a problem in processing a conventional UV-O3, by means of plasma process using O3 gas. Therefore, it can effectively remove defects of carbon and oxygen within the BST thin film and tantalum oxide film without complicating the process or deteriorating the electrical characteristic of the capacitor. The present invention also proposes a detailed process condition, which can optimize the plasma process using O3 gas.

摘要翻译： 公开了在非常高的集成存储器件中使用具有高介电特性的Ta2O5，BST（（Ba1-xSrx）TiO3）等作为电容器电介质膜的半导体器件的高介电电容器的方法。 本发明的目的是提供一种制造半导体器件的高介电电容器的方法，其可以有效地去除沉积BST膜之后的薄膜中包含的碳和沉积薄膜时引起的氧耗损缺陷， 其也可以在沉积氧化钽膜之后，除去薄膜中所含的碳和沉积薄膜所引起的氧耗尽的缺陷，而不需要进一步的困难处理或不会使电容器的电特性恶化。 通过形成具有良好反应性的等离子体O 3气体和通过处理BST薄膜和氧化钽膜的等离子体，采用能够有效地去除薄膜内的碳和氧缺乏的缺陷的技术。 因此，通过使用O 3气体的等离子体处理，可以延长氧气的活化氧的寿命，这在处理常规的UV-O 3中是一个问题。 因此，可以有效地去除BST薄膜和氧化钽膜内的碳和氧的缺陷，而不会使工艺复杂化或劣化电容器的电特性。 本发明还提出了一种详细的工艺条件，其可以优化使用O 3气体的等离子体工艺。

公开(公告)号：US5872047A

公开(公告)日：1999-02-16

申请号：US871850

申请日：1997-06-09

申请人： Kil Ho Lee ,  Sang Ho Yu

发明人： Kil Ho Lee ,  Sang Ho Yu

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823418

摘要： A method for forming a shallow junction of a semiconductor device, characterized by a rapid thermal process executed to considerably decrease the density of the point defects which may be caused by ion implantation. With it, a junction which is much shallower, with lower sheet resistance and less junction leakage current can be obtained even under conventional ion implantation and tube treatment conditions. This contributes to an improvement in the production yield of a semiconductor device. By virtue of the elimination of the point defects, the limits in selecting the tube thermal treatment temperature and time for planarizing the subsequent interlayer insulating film can be relieved, so that process allowance can be secured, thereby improving the reliability of the semiconductor device and allowing the high integration of the semiconductor device.

摘要翻译： 一种用于形成半导体器件的浅结的方法，其特征在于执行快速热处理以显着降低由离子注入引起的点缺陷的密度。 因此，即使在常规的离子注入和管处理条件下，也可以获得更浅的结，具有较低的薄层电阻和较少的结漏电流。 这有助于提高半导体器件的产量。 由于消除点缺陷，可以减轻选择用于平坦化后续层间绝缘膜的管热处理温度和时间的限制，从而可以确保工艺余量，从而提高半导体器件的可靠性并允许 半导体器件的高集成度。

公开(公告)号：US5683920A

公开(公告)日：1997-11-04

申请号：US768940

申请日：1996-12-18

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L27/092 ,  H01L21/335 ,  H01L21/8238

CPC分类号： H01L21/823814

摘要： A method for fabricating a semiconductor device which is capable of forming an ultra-shallow junction causing no defect in source/drain regions. The method includes the steps of providing a semiconductor substrate formed with n and p type wells and element-isolating films, forming gate oxide films on the n and p type wells, respectively, forming a polysilicon film over the entire exposed upper surface of the resulting structure, implanting first impurity ions having an n type conductivity in a portion of the polysilicon film disposed over the p type well, implanting first impurity ions having a p type conductivity in a portion of the polysilicon film disposed over the n type well, implanting second impurity ions having the p type conductivity in portions of the polysilicon film except for portions which will be used as gate electrodes, annealing the resulting structure in such a manner that the first impurity ions having the p type conductivity are diffused into the n type well, thereby forming p.sup.+ source/drain, selectively removing the polysilicon film, thereby forming n and p type gate electrodes, and implanting second impurity ions having the n type conductivity in an exposed surface portion of the p type well, thereby forming n.sup.+ source/drain.

摘要翻译： 一种制造半导体器件的方法，该半导体器件能够形成在源极/漏极区域中不产生缺陷的超浅结。 该方法包括以下步骤：提供形成有n型和p型阱和元件隔离膜的半导体衬底，分别在n型和p型阱上形成栅极氧化膜，在所得到的整个暴露的上表面上形成多晶硅膜 结构，在位于p型阱上的多晶硅膜的一部分中注入具有n型导电性的第一杂质离子，在第n型阱上设置多晶硅膜的部分中注入具有p型导电性的第一杂质离子，注入第二杂质 除了将用作栅电极的部分之外，在多晶硅膜的部分中具有p型导电性的离子，以使得具有p型导电性的第一杂质离子扩散到n型阱中的方式退火所得到的结构，从而 形成p +源极/漏极，选择性地去除多晶硅膜，由此形成n型和p型栅电极，以及植入第二阻挡层 y型离子在p型阱的露出表面部分具有n型导电性，从而形成n +源极/漏极。

公开(公告)号：US5677213A

公开(公告)日：1997-10-14

申请号：US604909

申请日：1996-02-22

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/285 ,  H01L21/225 ,  H01L21/336 ,  H01L21/266

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L29/41783 ,  H01L29/6659

摘要： In accordance with an aspect of the present invention, there is provided a method for forming a junction of a low sheet resistance on a silicon substrate, comprising the steps of forming an amorphous silicon layer on said silicon substrate; implanting impurity ions into said amorphous silicon layer; implanting transition metal ions into said amorphous silicon layer; and thermally treating said amorphous silicon layer and silicon substrate such that said transition metal ions diffuse to the surface of said silicon substrate and said impurity ions diffuse into said silicon substrate.

摘要翻译： 根据本发明的一个方面，提供了一种在硅衬底上形成低电阻的接合的方法，包括以下步骤：在所述硅衬底上形成非晶硅层; 将杂质离子注入所述非晶硅层; 将过渡金属离子注入所述非晶硅层; 以及热处理所述非晶硅层和硅衬底，使得所述过渡金属离子扩散到所述硅衬底的表面，并且所述杂质离子扩散到所述硅衬底中。

公开(公告)号：US6077734A

公开(公告)日：2000-06-20

申请号：US922358

申请日：1997-09-03

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/8232 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/2652 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/6659

摘要： The present invention is to provide a method for fabricating a semiconductor device which can minimize the defect density of the substrate, reduce the junction depth of the source/drain, and minimize the leakage current in the source/drain regions by implanting boron ions into the substrate in two steps which are different from each other by implant energy and implant dose.According to the invention, this method of fabricating semiconductor device comprises the steps of forming a gate oxide layer and a gate electrode on a semiconductor substrate or on a semiconductor substrate having N-well; implanting boron ions into the substrate at first and second ion implantation steps, the interstitial point defect region caused by the first ion implantation step overlapping with the vacancy point defect region caused by the second ion implantation step; and activating the boron implanted into the substrate by means of a subsequent thermal process to form source/drain regions.

摘要翻译： 本发明提供一种制造半导体器件的方法，其可以使衬底的缺陷密度最小化，减少源极/漏极的结深度，并且通过将硼离子注入到源极/漏极区域中来最小化源极/漏极区域中的漏电流 基板在两个步骤中通过植入能量和植入剂量彼此不同。 根据本发明，制造半导体器件的方法包括以下步骤：在半导体衬底上或在具有N阱的半导体衬底上形成栅极氧化物层和栅电极; 在第一和第二离子注入步骤中将硼离子注入到衬底中，由第一离子注入步骤引起的间隙点缺陷区域与由第二离子注入步骤引起的空位点缺陷区域重叠; 以及通过随后的热处理激活注入到衬底中的硼以形成源/漏区。

公开(公告)号：US5668020A

公开(公告)日：1997-09-16

申请号：US651856

申请日：1996-05-21

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/08

CPC分类号： H01L29/6659 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0847 ,  Y10S148/061

摘要： A method for forming impurity junction regions of a semiconductor device wherein impurity junction regions with a small depth are formed by selectively forming defecting regions and amorphous regions in a semiconductor substrate by an implantation of impurity ions with a large molecular weight, thereby achieving an improvement in the characteristics of the semiconductor device. The method includes the steps of forming a first photoresist film pattern on an active region portion of a semiconductor substrate, implanting first impurity ions in exposed portions of said semiconductor substrate using said first photoresist film pattern as a mask, thereby forming defecting regions, removing said first photoresist film pattern, forming a second photoresist film pattern on the exposed semiconductor surface portions except for the portion which was covered with said first photoresist film pattern, implanting second impurity ions in exposed portions of said semiconductor substrate using said second photoresist film pattern as a mask, thereby forming amorphous regions, removing said second photoresist film pattern, and implanting third impurity ions in said active region portion of said semiconductor substrate, thereby forming impurity junction regions.

摘要翻译： 一种用于形成半导体器件的杂质结区的方法，其中通过以大分子量注入杂质离子选择性地在半导体衬底中形成缺陷区域和非晶区域，形成具有较小深度的杂质结区域，从而实现了改进 半导体器件的特性。 该方法包括以下步骤：在半导体衬底的有源区部分上形成第一光致抗蚀剂图案，使用所述第一光致抗蚀剂膜图案作为掩模，将所述半导体衬底的暴露部分中的第一杂质离子注入，从而形成缺陷区， 第一光致抗蚀剂膜图案，在暴露的半导体表面部分上形成第二光致抗蚀剂图案，除了被所述第一光致抗蚀剂膜图案覆盖的部分之外，使用所述第二光致抗蚀剂膜图案将所述第二光致抗蚀剂膜图案的第二杂质离子注入 从而形成非晶区域，去除所述第二光致抗蚀剂膜图案，以及在所述半导体衬底的所述有源区域部分中注入第三杂质离子，由此形成杂质结区域。