公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

Applicant: Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

Inventor： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11543

Abstract: A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

Abstract translation: 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US5932492A

公开(公告)日：1999-08-03

申请号：US731955

申请日：1996-10-23

Applicant: Jin-hwan Hahm ,  Kyeong-koo Chi

Inventor： Jin-hwan Hahm ,  Kyeong-koo Chi

IPC: C23F1/00 ,  C23C8/10 ,  C23C8/80 ,  H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  B44C1/22

CPC classification number: H01L28/40 ,  C23C8/10 ,  C23C8/80 ,  H01L21/31144 ,  H01L21/31683

Abstract: A method for forming a capacitor structure includes the steps of forming a conductive layer in a substrate, and forming a dielectric layer on the conductive layer opposite the substrate. An aluminum layer is formed on the dielectric layer, and this aluminum layer is patterned so that portions of the dielectric layer are exposed. The patterned aluminum layer is then oxidized to form an alumina masking layer. The alumina masking layer can then be used to selectively etch portions of the dielectric and conductive layers exposed thereby. Related systems are also disclosed.

Abstract translation: 形成电容器结构的方法包括以下步骤：在衬底中形成导电层，并在与衬底相对的导电层上形成电介质层。 在电介质层上形成铝层，对该铝层进行图案化，使电介质层的一部分露出。 然后将图案化的铝层氧化以形成氧化铝掩蔽层。 氧化铝掩模层然后可用于选择性地蚀刻由此暴露的电介质层和导电层的部分。 还公开了相关系统。

公开(公告)号：US5859501A

公开(公告)日：1999-01-12

申请号：US818256

申请日：1997-03-14

Applicant: Kyeong-koo Chi

Inventor： Kyeong-koo Chi

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H03B28/00 ,  H05H1/46

CPC classification number: H05H1/46

Abstract: A radio frequency (RF) generating system for forming pulse plasma utilizes a plasma reaction device comprises a function generator, an amplifier, and an input port. The function generator generates a signal of time-modulated RF power according to a modulation function having a waveform, wherein the waveform gradually ascends at a rising edge and gradually descends at a falling edge. The input port receives the signal from the function generator and transmits the signal to the amplifier. The amplifier amplifies the signal to a predetermined level and then transmits the amplified signal to the plasma reaction device. A method for forming pulse plasma comprises the steps of generating a time-modulated RF power signal according to a modulation function having a waveform, wherein the waveform is shaped to gradually ascend at a rising edge and to gradually descend at a falling edge, amplifying the time-modulated RF power signal to a predetermined level, and transmitting the amplified time-modulated RF power signal to a plasma reaction device. In an embodiment of the present invention, the waveform is a half sine waveform, though other suitable waveforms include a half cosine waveform and a Gaussian pulse signal.

Abstract translation: 用于形成脉冲等离子体的射频（RF）生成系统利用等离子体反应装置，其包括功能发生器，放大器和输入端口。 函数发生器根据具有波形的调制函数产生时间调制的RF功率的信号，其中波形在上升沿逐渐上升，并且在下降沿逐渐下降。 输入端口接收来自函数发生器的信号，并将该信号发送到放大器。 放大器将信号放大到预定电平，然后将放大的信号传输到等离子体反应装置。 用于形成脉冲等离子体的方法包括以下步骤：根据具有波形的调制函数产生时间调制的RF功率信号，其中波形被成形为在上升沿逐渐上升并且在下降沿逐渐下降， 时间调制的RF功率信号到预定电平，并且将放大的经时间调制的RF功率信号发送到等离子体反应装置。 在本发明的一个实施例中，波形是半正弦波形，尽管其它合适的波形包括半余弦波形和高斯脉冲信号。

公开(公告)号：US07709389B2

公开(公告)日：2010-05-04

申请号：US11480545

申请日：2006-07-05

Applicant: Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

Inventor： Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816 ,  H01L21/76897 ,  Y10S438/947

Abstract: A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.

Abstract translation: 公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。 制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

公开(公告)号：US07052952B2

公开(公告)日：2006-05-30

申请号：US10779494

申请日：2004-02-13

Applicant: In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

Inventor： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

IPC: H01L21/8242

CPC classification number: H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10855 ,  Y10S438/978

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract translation: 通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。 图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。 在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。 在与半导体衬底电连接的沟槽中形成位线。 形成覆盖位线的第二绝缘层。 第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

公开(公告)号：US6159811A

公开(公告)日：2000-12-12

申请号：US857754

申请日：1997-05-15

Applicant: Hwa-sook Shin ,  Kyeong-koo Chi ,  Chan-ouk Jung

Inventor： Hwa-sook Shin ,  Kyeong-koo Chi ,  Chan-ouk Jung

IPC: H01L21/28 ,  H01L21/3213 ,  H10L21/336

CPC classification number: H01L21/32137 ,  H01L21/28061

Abstract: A method for forming a gate structure on a semiconductor substrate includes the following steps. A layer of a gate material is formed on the semiconductor substrate, and a patterned mask layer is formed on the layer of the gate material opposite the substrate. The layer of the gate material is then etched with an etching gas including a mixture of chlorine gas (Cl.sub.2), oxygen gas (O.sub.2), and a gas including fluorine (F) using the patterned mask layer as an etching mask. In particular, the step of forming the layer of the gate material can include the steps of forming a polysilicon layer on a surface of the semiconductor substrate, and forming a silicide layer on the polysilicon layer opposite the substrate.

Abstract translation: 在半导体衬底上形成栅极结构的方法包括以下步骤。 在半导体衬底上形成栅极材料层，并且在与衬底相对的栅极材料层上形成图案化掩模层。 然后使用图案化掩模层作为蚀刻掩模，用包括氯气（Cl2），氧气（O2）和包括氟（F）的气体的混合物的蚀刻气体蚀刻栅极材料层。 特别地，形成栅极材料层的步骤可以包括以下步骤：在半导体衬底的表面上形成多晶硅层，并在与衬底相对的多晶硅层上形成硅化物层。

公开(公告)号：US20070082296A1

公开(公告)日：2007-04-12

申请号：US11545417

申请日：2006-10-10

Applicant: Song-yi Yang ,  Kyeong-koo Chi

Inventor： Song-yi Yang ,  Kyeong-koo Chi

IPC: G03C5/00

CPC classification number: H01L21/31144 ,  G03F7/0035 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139

Abstract: Provided is a method of forming micro-patterns using a multi-photolithography process, including: providing an etch target layer where micro-patterns are to be formed; forming a mask layer on the etch target layer; forming a first mask pattern including engraved portions and embossed portions by etching a predetermined region of the mask layer; forming a final mask pattern in the first mask pattern by etching a predetermined region of the residual embossed portions of the mask layer; and forming micro-patterns by etching the etch target layer using the final mask pattern as an etch mask.

Abstract translation: 提供了使用多光刻工艺形成微图案的方法，包括：提供要形成微图案的蚀刻目标层; 在蚀刻目标层上形成掩模层; 通过蚀刻掩模层的预定区域形成包括雕刻部分和压花部分的第一掩模图案; 通过蚀刻掩模层的残留压花部分的预定区域，在第一掩模图案中形成最终掩模图案; 以及通过使用最终掩模图案作为蚀刻掩模蚀刻蚀刻目标层来形成微图案。

公开(公告)号：US20060284277A1

公开(公告)日：2006-12-21

申请号：US11510349

申请日：2006-08-25

Applicant: Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

Inventor： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

IPC: H01L29/00

CPC classification number: H01L27/10885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

Abstract translation: 半导体器件包括：绝缘层，其具有由窄开口重叠的宽开口形成的T形槽，至少部分填充窄开口的位线导电层和填充槽的位线封盖层，使得其 顶表面与绝缘层一样高。 隔板形成在宽开口的内壁上。

公开(公告)号：US20050287738A1

公开(公告)日：2005-12-29

申请号：US11159130

申请日：2005-06-23

Applicant: Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

Inventor： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract translation: 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US20050266648A1

公开(公告)日：2005-12-01

申请号：US11109292

申请日：2005-04-19

Applicant: Sung-hoon Chung ,  Byeong-yun Nam ,  Kyeong-koo Chi

Inventor： Sung-hoon Chung ,  Byeong-yun Nam ,  Kyeong-koo Chi

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/10876

Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Abstract translation: 形成场效应晶体管的方法包括在半导体衬底上形成第一电绝缘层的步骤，该半导体衬底上具有限定其间的有源区的多个沟槽隔离区。 然后将第一电绝缘层图案化以限定其中与活动区域相对延伸的第一多个开口。 然后通过用电绝缘塞填充第一多个开口然后使用电绝缘插塞作为蚀刻掩模来蚀刻图案化的第一电绝缘层，形成其中具有第二多个开口的沟槽掩模。 然后通过使用沟槽掩模作为蚀刻掩模蚀刻半导体衬底，在有源区中形成多个沟槽。 然后形成延伸到多个沟槽中的多个绝缘栅电极。