公开(公告)号：US20100323525A1

公开(公告)日：2010-12-23

申请号：US12809021

申请日：2008-12-09

申请人： Kyeong-Koo Chi ,  Jonathan Kim

发明人： Kyeong-Koo Chi ,  Jonathan Kim

IPC分类号： H01L21/3065

CPC分类号： H01L21/31144 ,  H01L21/0276

摘要： A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.

摘要翻译： 提供了一种用于蚀刻设置在图案化掩模下面的抗反射涂层（ARC）层下方的蚀刻层中的线图案的方法。 该方法包括：在其中设置包括CF 3I的ARC开口气体，含有气体的碳氟化合物（包括氢氟烃）和含氧气体的ARC层，从ARC开口气体形成等离子体以打开ARC层，并且 提供ARC打开气体停止。 线图案特征通过打开的ARC层蚀刻到蚀刻层中。

公开(公告)号：US07510934B2

公开(公告)日：2009-03-31

申请号：US11807544

申请日：2007-05-29

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

公开(公告)号：US20080188081A1

公开(公告)日：2008-08-07

申请号：US11671340

申请日：2007-02-05

申请人： Kyeong-Koo Chi ,  Erik A. Edelberg

发明人： Kyeong-Koo Chi ,  Erik A. Edelberg

IPC分类号： H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76816

摘要： A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.

摘要翻译： 提供了一种通过碳基掩模蚀刻介电层中的超高宽比特征的方法。 相对于碳基掩模选择性地蚀刻电介质层，其中选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。 选择性蚀刻停止。 相对于碳基掩模选择性地除去氟碳聚合物，使得使用修整保留碳基掩模。 停止选择性除去氟碳聚合物。 相对于碳基掩模再次选择性地蚀刻介电层，其中第二选择性蚀刻提供基于碳基掩模的碳氟基聚合物的净沉积。

公开(公告)号：US07402488B2

公开(公告)日：2008-07-22

申请号：US11159130

申请日：2005-06-23

申请人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

发明人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

摘要翻译： 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07338849B2

公开(公告)日：2008-03-04

申请号：US11261820

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

摘要翻译： 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US07303957B2

公开(公告)日：2007-12-04

申请号：US11517254

申请日：2006-09-08

申请人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

发明人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

公开(公告)号：US07242054B2

公开(公告)日：2007-07-10

申请号：US11190314

申请日：2005-07-26

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L29/788 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

公开(公告)号：US20070059876A1

公开(公告)日：2007-03-15

申请号：US11517254

申请日：2006-09-08

申请人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

发明人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

摘要翻译： 提供了一种使用用于形成自对准浮动栅极的工艺来制造闪速存储器件的方法。 该方法包括在衬底上形成掩模图案，使用掩模图案蚀刻衬底作为蚀刻掩模以形成多个沟槽，并用第一绝缘层填充沟槽，其中掩模图案的侧壁在填充沟槽之后保持暴露 与第一绝缘层。 该方法还包括在掩模图案的暴露的侧壁上形成间隔物，用第二绝缘层填充上绝缘空间，从而限定隔离层，以及去除掩模图案和间隔物。