Abstract:
A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.
Abstract:
To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.
Abstract:
A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.
Abstract:
A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.
Abstract:
To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.
Abstract:
A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.
Abstract:
A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
Abstract:
Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.
Abstract:
A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.
Abstract:
Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.