公开(公告)号：US08124538B2

公开(公告)日：2012-02-28

申请号：US12422108

申请日：2009-04-10

Applicant: In Deog Bae ,  Qian Fu ,  Wonchul Lee ,  Shenjian Liu

Inventor： In Deog Bae ,  Qian Fu ,  Wonchul Lee ,  Shenjian Liu

IPC: H01L21/302

CPC classification number: H01L21/31122

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract translation: 提供了一种相对于多晶硅材料选择性地蚀刻高k电介质层的方法。 通过Ar溅射部分去除高k电介质层，然后使用包含BCl 3的蚀刻气体蚀刻高k电介质层。 高k电介质层和多晶硅材料可以形成在衬底上。 为了部分去除高k电介质层，将含有Ar的溅射气体设置在其中放置基板的蚀刻室中，从溅射气体产生等离子体，然后停止溅射气体。 为了蚀刻高k电介质层，蚀刻气体被提供到蚀刻室中，从蚀刻气体产生等离子体，然后停止蚀刻气体。

公开(公告)号：US20050199920A1

公开(公告)日：2005-09-15

申请号：US11076185

申请日：2005-03-09

Applicant: Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

Abstract translation: 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

公开(公告)号：US20090258502A1

公开(公告)日：2009-10-15

申请号：US12422108

申请日：2009-04-10

Applicant: In Deog BAE ,  Qian FU ,  Wonchul LEE ,  Shenjian LIU

Inventor： In Deog BAE ,  Qian FU ,  Wonchul LEE ,  Shenjian LIU

IPC: H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/31122

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract translation: 提供了一种相对于多晶硅材料选择性地蚀刻高k电介质层的方法。 通过Ar溅射部分去除高k电介质层，然后使用包含BCl 3的蚀刻气体蚀刻高k电介质层。 高k电介质层和多晶硅材料可以形成在衬底上。 为了部分去除高k电介质层，将含有Ar的溅射气体设置在其中放置基板的蚀刻室中，从溅射气体产生等离子体，然后停止溅射气体。 为了蚀刻高k电介质层，蚀刻气体被提供到蚀刻室中，从蚀刻气体产生等离子体，然后停止蚀刻气体。

公开(公告)号：US07385237B2

公开(公告)日：2008-06-10

申请号：US11076185

申请日：2005-03-09

Applicant: Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

Abstract translation: 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

公开(公告)号：US07052952B2

公开(公告)日：2006-05-30

申请号：US10779494

申请日：2004-02-13

Applicant: In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

Inventor： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

IPC: H01L21/8242

CPC classification number: H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10855 ,  Y10S438/978

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract translation: 通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。 图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。 在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。 在与半导体衬底电连接的沟槽中形成位线。 形成覆盖位线的第二绝缘层。 第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。