知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.021 seconds)

    Memory controller, storage device and decoding method
    1.
    发明授权
    Memory controller, storage device and decoding method 有权

    公开(公告)号：US09600364B2

    公开(公告)日：2017-03-21

    申请号：US14832023

    申请日：2015-08-21

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Osamu Torii ,  Haruka Obata ,  Ryo Yamaki ,  Daiki Watanabe

    IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29

    CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/2909

    Abstract: According to an embodiment, a row decoder to perform row decoding by using, as row soft input information, a row received word read as soft determination information from a non-volatile memory and to calculate row extrinsic information and a column decoder to perform column decoding by using column soft input information, which is a result of adding of the row extrinsic information to a column received word read as soft determination information from the non-volatile memory, and to calculate column extrinsic information are included. The row decoder includes a first decoder for first decoding, a second decoder for second decoding a decoding method of which is different from that of the first decoding, and a selection unit to select a decoded result based on accuracy of a decoded result of the first decoding and that of a decoded result of the second decoding and to calculate the row extrinsic information.

    Memory controller, storage device and memory control method
    2.
    发明授权
    Memory controller, storage device and memory control method 有权
    内存控制器，存储设备和内存控制方式

    公开(公告)号：US09077381B2

    公开(公告)日：2015-07-07

    申请号：US13950753

    申请日：2013-07-25

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Naoaki Kokubun ,  Osamu Torii ,  Toshikatsu Hida

    IPC: H03M13/00 ,  H03M13/15 ,  H03M13/35

    CPC classification number: H03M13/151 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/35

    Abstract: According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.

    Abstract translation: 根据一个实施例，存储器控制器包括对输入数据执行纠错编码处理并产生码字的编码单元，控制是否执行乘法电路的乘法运算的计算控制单元和存储器接口 控制代码字写入存储器并从存储器读取代码字的单元，编码单元包括使用第一生成多项式对输入数据执行余数计算的余数电路，并生成第一代码字 具有第一纠错能力和第一乘法电路，其使用第二生成多项式对所述第一码字进行乘法运算，并执行产生具有第二纠错能力的第二码字的乘法计算。

    Memory system
    3.
    发明授权
    Memory system 有权

    公开(公告)号：US09761325B1

    公开(公告)日：2017-09-12

    申请号：US15068938

    申请日：2016-03-14

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Juan Shi ,  Hironori Uchikawa ,  Tokumasa Hara ,  Osamu Torii

    IPC: G11C29/00 ,  G11C29/02 ,  G11C7/00

    CPC classification number: G11C29/021 ,  G11C29/42

    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.

    STORAGE DEVICE, MEMORY CONTROLLER AND MEMORY CONTROL METHOD
    4.
    发明申请
    STORAGE DEVICE, MEMORY CONTROLLER AND MEMORY CONTROL METHOD 审中-公开
    存储设备，存储器控制器和存储器控制方法

    公开(公告)号：US20160071597A1

    公开(公告)日：2016-03-10

    申请号：US14624938

    申请日：2015-02-18

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Naoaki KOKUBUN ,  Osamu Torii ,  Riki Suzuki

    IPC: G11C16/10 ,  G06F11/10 ,  G11C16/26

    CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3495 ,  G11C2211/5641

    Abstract: According to an embodiment, a storage device includes a nonvolatile memory which includes a plurality of memory cells and a memory controller which controls writing on the nonvolatile memory. In a case where an exhaustion degree of the memory cell of the nonvolatile memory is less than a threshold, the memory controller performs a fractional-bit writing in which the number of threshold regions of the memory cell is set to Z (where, Z is a positive value not a power of two). In a case where the exhaustion degree of the memory cell is equal to or higher than the threshold, the memory controller performs an integer-bit writing in which the number of threshold regions of the memory cell is set to 2m (where, 2m is smaller than Z).

    Abstract translation: 根据实施例，存储装置包括包括多个存储单元的非易失性存储器和控制对非易失性存储器的写入的存储器控​​制器。 在非易失性存储器的存储单元的耗尽度小于阈值的情况下，存储器控制器执行将存储单元的阈值区域的数量设定为Z（其中，Z为 一个正值不是二的幂）。 在存储单元的耗尽程度等于或高于阈值的情况下，存储器控制器执行将存储单元的阈值区域的数量设置为2m（其中，2m更小）的整数位写入 比Z）。

    Storage device, memory controller and memory control method
    5.
    发明授权
    Storage device, memory controller and memory control method 有权
    存储设备，内存控制器和内存控制方式

    公开(公告)号：US09171629B1

    公开(公告)日：2015-10-27

    申请号：US14478292

    申请日：2014-09-05

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Naoaki Kokubun ,  Osamu Torii ,  Kohsuke Harada ,  Riki Suzuki

    IPC: G11C11/34 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C2211/5641

    Abstract: According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2n, of threshold areas can be set in the memory cells of the nonvolatile memory. The memory controller performs first writing based on first data value assignment, which sets 2n data values to correspond to 2n threshold areas, in first-time writing into a first memory cell of the nonvolatile memory and performs second writing on the first memory cell after the first writing without erasing data based on second data value assignment, which sets 2n data values to correspond to 2n threshold areas including threshold areas not used in the first data value assignment.

    Abstract translation: 根据一个实施例，存储设备包括非易失性存储器和执行从非易失性存储器读取数据和向非易失性存储器写入数据的存储器控​​制器。 可以在非易失性存储器的存储单元中设置不是2n的阈值区域的数目。 存储器控制器基于第一数据值分配执行首次写入，其首先将2n个数据值设置为对应于2n个阈值区域，首次写入到非易失性存储器的第一存储单元中，并且在第一存储器单元之后执行第二写入 首先写入而不擦除基于第二数据值分配的数据，其将2n个数据值设置为对应于包括在第一数据值分配中未使用的阈值区域的2n个阈值区域。

    MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD
    6.
    发明申请
    MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD 有权
    存储器控制器，存储器系统和存储器控制方法

    公开(公告)号：US20150254134A1

    公开(公告)日：2015-09-10

    申请号：US14446463

    申请日：2014-07-30

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Riki SUZUKI ,  Toshikatsu Hida ,  Osamu Torii ,  Hiroshi Yao ,  Kiyotaka Iwasaki

    IPC: G06F11/10 ,  G11C29/14

    CPC classification number: H03M13/35 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11B20/1833 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957

    Abstract: According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.

    Abstract translation: 根据一个实施例，存储器控制器包括：确定用户数据的写入目的地的写入目的地管理单元，产生用户数据的奇偶校验的编码单元;以及测量每个特定存储区域的疲劳程度的ECC管理单元 选择编码方法来指示根据编码方法执行编码单元，并且在对应于写入目的地的疲劳度的情况下，将编码方法改变为具有高纠错能力的编码方法 等于或高于阈值，并且奇偶校验的总和等于或小于预定量。

    Memory controller
    7.
    发明授权
    Memory controller 有权
    内存控制器

    公开(公告)号：US08954828B2

    公开(公告)日：2015-02-10

    申请号：US13841923

    申请日：2013-03-15

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Osamu Torii ,  Shinichi Kanno ,  Ryo Yamaki

    IPC: H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H03M13/29

    CPC classification number: H03M13/09 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/2906

    Abstract: According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i−1)-th parities.

    Abstract translation: 根据实施例，存储器控制器包括：编码单元，用于对用户数据执行纠错编码处理以产生第一至第n个奇偶校验，并对第一至第n个奇偶校验中的每一个进行纠错编码处理，以产生 第一到第n外部平等; 以及解码单元，其使用用户数据，第一至第n个奇偶校验和第一至第n个外部奇偶校验来执行纠错解码处理。 基于用于生成第一至第（i-1）个奇偶校验的生成多项式来选择用于生成第i个奇偶校验的生成多项式。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09548107B1

    公开(公告)日：2017-01-17

    申请号：US14963482

    申请日：2015-12-09

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Naoko Kifune ,  Masanobu Shirakawa ,  Ryo Yamaki ,  Osamu Torii

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

    CPC classification number: G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5648

    Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.

    Abstract translation: 半导体存储器件包括被配置为根据阈值保持4位数据的存储器单元。 通过使用第一至第三读取电平读取操作来建立4位数据的第一位。 通过使用第四到第七读取电平的读取操作来建立与第一位不同的第二位。 通过使用第八到第十一读取电平的读取操作来建立与第一和第二位不同的第三位。 通过使用第十二至第十五读取电平的读取操作来建立与第一至第三位不同的第四位。

Patent Agency Ranking