公开(公告)号：US06265274B1

公开(公告)日：2001-07-24

申请号：US09431954

申请日：1999-11-01

申请人： Jui-Tsen Huang ,  Chien-Hua Tsai

发明人： Jui-Tsen Huang ,  Chien-Hua Tsai

IPC分类号： H01L21336

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/66553 ,  H01L29/6659

摘要： A semiconductor wafer comprises a silicon substrate, and a dielectric layer. A gate is formed on the dielectric layer. A first silicon oxide layer is uniformly formed on the semiconductor wafer. A first ion implantation process is performed to form two doped areas on the silicon substrate that are used as two lightly doped drains of a MOS transistor. A second silicon oxide layer is formed on the semiconductor wafer. A sacrificial layer is formed on the second silicon oxide layer. A first etching process is performed to remove the sacrificial layer on top of the gate, causing the gate to protrude from the remaining sacrificial layer for a predetermined height. A second etching process is performed to remove the first and second silicon oxide layers on the protruding portion of the gate. After removing the sacrificial layer completely, a silicon nitride layer is uniformly formed on the semiconductor wafer. A third etching process is performed to vertically remove the silicon nitride layer on top of the gate, thereby forming a spacer. Finally, a second ion implantation process is performed to form two doped areas on the silicon substrate, which are used as source and drain of the MOS transistor.

摘要翻译： 半导体晶片包括硅衬底和电介质层。 在电介质层上形成栅极。 在半导体晶片上均匀地形成第一氧化硅层。 执行第一离子注入工艺以在硅衬底上形成用作MOS晶体管的两个轻掺杂漏极的两个掺杂区域。 在半导体晶片上形成第二氧化硅层。 牺牲层形成在第二氧化硅层上。 执行第一蚀刻工艺以去除栅极顶部上的牺牲层，导致栅极从剩余牺牲层突出预定高度。 执行第二蚀刻工艺以去除栅极的突出部分上的第一和第二氧化硅层。 在完全去除牺牲层之后，在半导体晶片上均匀地形成氮化硅层。 执行第三蚀刻工艺以垂直去除栅极顶部上的氮化硅层，从而形成间隔物。 最后，进行第二离子注入工艺以在硅衬底上形成用作MOS晶体管的源极和漏极的两个掺杂区域。

公开(公告)号：US20060024921A1

公开(公告)日：2006-02-02

申请号：US10710662

申请日：2004-07-27

申请人： Jui-Tsen Huang

发明人： Jui-Tsen Huang

IPC分类号： H01L21/46

CPC分类号： H01L23/562 ,  H01L21/76801 ,  H01L21/76822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

摘要： A method of relieving wafer stress is provided. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the wafer has a first and a second area. At least no circuits are formed on the dielectric layer within the first area. Thereafter, openings are formed in the dielectric layer within the first area. A material layer is formed over the dielectric layer. Thus, pits are formed on the surface of the material layer at locations above the openings. Through the pits on the material layer, stress within the material layer is relieved and hence the amount of stress conferred to the wafer is reduced.

摘要翻译： 提供了一种减轻晶片应力的方法。 提供晶片，其中已经在晶片上形成至少一个电介质层，并且晶片具有第一和第二区域。 在第一区域内的电介质层上至少不形成电路。 此后，在第一区域内的电介质层中形成开口。 在电介质层上形成材料层。 因此，在开口上方的位置处，在材料层的表面上形成凹坑。 通过材料层上的凹坑，材料层内的应力得以缓解，因此赋予晶片的应力量减少。

公开(公告)号：US06242334B1

公开(公告)日：2001-06-05

申请号：US09274597

申请日：1999-03-23

申请人： Michael Wei-Che Huang ,  Jui-Tsen Huang ,  Ling Lu ,  Tri-Rung Yew

发明人： Michael Wei-Che Huang ,  Jui-Tsen Huang ,  Ling Lu ,  Tri-Rung Yew

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656

摘要： A method for forming a semiconductor with overetched spacer is disclosed. The method includes firstly providing a semiconductor substrate with a gate oxide layer formed thereon, and forming a polysilicon layer on the gate oxide layer. Next, a photoresist layer is formed on the polysilicon layer to define a gate area, followed by anisotropically etching the polysilicon layer and the gate oxide layer. A first dielectric layer is conformably formed, and a second dielectric layer is then formed thereon. After anisotropically etching the second dielectric layer to form a first sidewall spacer on the sidewall of the first dielectric layer, a third dielectric layer is further formed over the exposed first dielectric layer and the first sidewall spacer. Finally, the third dielectric layer and the first sidewall spacer are anisotropically etched so that a second sidewall spacer is formed on the sidewall of the first sidewall spacer, wherein top surface of the first and the second sidewall spacer is below top surface of the first dielectric layer around the gate area.

摘要翻译： 公开了一种用椭圆形间隔物形成半导体的方法。 该方法包括首先提供其上形成有栅极氧化物层的半导体衬底，并在栅极氧化物层上形成多晶硅层。 接下来，在多晶硅层上形成光致抗蚀剂层以限定栅极区域，然后各向异性蚀刻多晶硅层和栅极氧化物层。 顺应地形成第一电介质层，然后在其上形成第二电介质层。 在各向异性蚀刻第二电介质层以在第一介电层的侧壁上形成第一侧壁间隔物之后，在暴露的第一介电层和第一侧壁间隔物上进一步形成第三电介质层。 最后，第三介电层和第一侧壁间隔物被各向异性地蚀刻，使得第二侧壁间隔物形成在第一侧壁间隔物的侧壁上，其中第一和第二侧壁间隔物的顶表面在第一电介质的顶表面下方 层围绕门区。

公开(公告)号：US20100103611A1

公开(公告)日：2010-04-29

申请号：US12534859

申请日：2009-08-04

申请人： Ching-Fu Yang ,  You-Chi Liu ,  Kuo-Nan Ling ,  Po-An Lin ,  Yung-Hui Chen ,  Hao-Ying Chang ,  Jui-Tsen Huang

发明人： Ching-Fu Yang ,  You-Chi Liu ,  Kuo-Nan Ling ,  Po-An Lin ,  Yung-Hui Chen ,  Hao-Ying Chang ,  Jui-Tsen Huang

IPC分类号： H05K7/00

CPC分类号： G06F1/169 ,  G06F1/1616 ,  G06F3/03547 ,  G06F3/0414

摘要： An electronic device having a touching function, including a touching region, a housing, a touch module, and a switch module is provided. The touching region is performing the touching function. The touching region is located over the housing. The touch module is disposed in the housing in correspondence with the touching region. The switch module includes at least one switch and is disposed under the touch module. The touch module is bent under force to turn on the switch when the touching region is touched.

摘要翻译： 提供具有触摸功能的电子设备，包括触摸区域，外壳，触摸模块和开关模块。 触摸区域正在执行触摸功能。 触摸区域位于外壳上方。 触摸模块与触摸区域对应地设置在壳体中。 开关模块包括至少一个开关并设置在触摸模块下方。 当触摸区域被触摸时，触摸模块在力下弯曲以打开开关。

公开(公告)号：US20090317560A1

公开(公告)日：2009-12-24

申请号：US12549342

申请日：2009-08-27

申请人： Yi-Ching Lee ,  Jui-Tsen Huang ,  Po-Tau Liu ,  Chan-Ming Liu

发明人： Yi-Ching Lee ,  Jui-Tsen Huang ,  Po-Tau Liu ,  Chan-Ming Liu

IPC分类号： C08J7/18 ,  C08J3/28

CPC分类号： C09D1/00 ,  C08K5/5419 ,  C09D7/63

摘要： A method of forming an ultraviolet curable paint coating is provided. First, an ultraviolet curable paint composition is formed by mixing, based on 100 parts by weight of the ultraviolet curable paint composition, 1 to 10 parts by weight of a photo-initiator, 5 to 20 parts by weight of an organosilane compound, 5 to 30 parts by weight of a binding agent, 0.1 to 15 parts by weight of a catalyst, and an ultraviolet curable resin, wherein a number of the functional group of the binding agent is more than that of the organosilane compound. Thereafter, a sub coating is formed by using the ultraviolet curable paint composition, and an ultraviolet curable paint coating is then formed by contacting the sub coating with a paint, wherein the unreacted hydroxyls of the sub coating react with the paint to facilitate the paint to adhere to a surface of the sub coating.

摘要翻译： 提供了形成紫外线固化涂料的方法。 首先，通过将100重量份的紫外线固化性涂料组合物，1〜10重量份的光引发剂，5〜20重量份的有机硅烷化合物，5〜5重量份， 30重量份的粘合剂，0.1〜15重量份的催化剂和紫外线固化性树脂，其中粘合剂的官能团数多于有机硅烷化合物的官能团数。 此后，通过使用紫外线固化涂料组合物形成副涂层，然后通过使副涂层与涂料接触而形成紫外线固化涂料涂层，其中副涂层的未反应羟基与涂料反应以促进涂料 粘附在底层的表面上。

公开(公告)号：US20060183031A1

公开(公告)日：2006-08-17

申请号：US11380192

申请日：2006-04-25

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US07063923B2

公开(公告)日：2006-06-20

申请号：US10711198

申请日：2004-09-01

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F9/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US20050277301A1

公开(公告)日：2005-12-15

申请号：US11196275

申请日：2005-08-04

申请人： Jui-Tsen Huang ,  Kuei-Chun Hung

发明人： Jui-Tsen Huang ,  Kuei-Chun Hung

IPC分类号： H01L21/311 ,  H01L21/3115 ,  H01L21/312 ,  H01L21/461

CPC分类号： H01L21/02282 ,  H01L21/02118 ,  H01L21/31133 ,  H01L21/31155 ,  H01L21/312

摘要： A method for forming a plane structure. It comprises the following steps: forms a liquid material with a thicker thickness on a substrate, rotating both the liquid material and the substrate around the axis of the substrate, applying a solvent on the rotating liquid material to remove partial liquid material. It also comprises the following steps: form a thicker removable material on a substrate, and partially remove the surface part of the removable material.

摘要翻译： 一种用于形成平面结构的方法。 它包括以下步骤：在基板上形成厚度较厚的液体材料，使液体材料和基板围绕基板的轴线旋转，在旋转的液体材料上施加溶剂以除去部分液体材料。 它还包括以下步骤：在基底上形成较厚的可移除材料，并部分地去除可移除材料的表面部分。

公开(公告)号：US06440861B1

公开(公告)日：2002-08-27

申请号：US09652471

申请日：2000-08-31

申请人： Chih-Chien Liu ,  Jui-Tsen Huang ,  Yi-Fang Cheng ,  Ming-Sheng Yang

发明人： Chih-Chien Liu ,  Jui-Tsen Huang ,  Yi-Fang Cheng ,  Ming-Sheng Yang

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1063

摘要： A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer.

摘要翻译： 形成双镶嵌结构的方法。 第一电介质层和第二电介质层依次形成在衬底上。 在第二介电层上形成第一光致抗蚀剂层。 进行光刻和蚀刻操作以去除第二介电层和第一介电层的一部分，从而形成通孔。 保形第三电介质层涂覆在第二电介质层的表面和通孔开口的内表面上。 保形第三电介质层形成衬里电介质层。 在第二电介质层上形成第二光致抗蚀剂层，然后对第二光致抗蚀剂层进行图案化。 使用图案化的第二光致抗蚀剂层作为掩模，去除第二介电层的一部分以形成沟槽。 去除图案化的第二光致抗蚀剂层。 导电材料沉积在衬底上以填充通孔和沟槽。 最后，进行化学机械抛光以除去第二介电层上方的多余的导电材料。

公开(公告)号：US07718345B2

公开(公告)日：2010-05-18

申请号：US12102029

申请日：2008-04-14

申请人： Jui-Tsen Huang

发明人： Jui-Tsen Huang

IPC分类号： G03F7/00 ,  G03F7/09 ,  G03F7/20 ,  G03F7/36 ,  G03F7/48

CPC分类号： H01L21/02118 ,  G03F7/091 ,  G03F7/11 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/312 ,  Y10S430/143 ,  Y10S430/151

摘要： A composite photoresist structure includes a first organic layer disposed over a substrate to be etched, a sacrificial layer disposed on the first organic layer, and a second organic layer disposed on the sacrificial layer. The thickness of the first organic layer and the thickness of the second organic layer are both larger than the thickness of the sacrificial layer.

摘要翻译： 复合光致抗蚀剂结构包括设置在待蚀刻的衬底上的第一有机层，设置在第一有机层上的牺牲层和设置在牺牲层上的第二有机层。 第一有机层的厚度和第二有机层的厚度均大于牺牲层的厚度。