公开(公告)号：US08161320B2

公开(公告)日：2012-04-17

申请号：US11606900

申请日：2006-12-01

申请人： Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

发明人： Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7204

摘要： An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

摘要翻译： 提供了一种设备，存储器件控制器和控制存储器件的方法。 该示例设备可以包括坏块位图参考单元，其被配置为基于给定的存储器地址从坏块位图获得坏块信息，给定存储器地址是与逻辑存储器对应的逻辑存储器地址之一和物理存储器地址 指示与给定存储器地址相对应的给定存储块是否为坏块的坏块信息和被配置为获得与逻辑存储器地址对应的物理存储器地址的存储器映射单元，并且被配置为获得预留的物理存储器地址 对应于物理存储器地址，如果坏块信息指示给定的存储器块是坏块。 在一个示例中，该装置可以被实现为包括闪存转换层（FTL）的存储器件控制器。

公开(公告)号：US20080155317A1

公开(公告)日：2008-06-26

申请号：US11606900

申请日：2006-12-01

申请人： Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

发明人： Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7204

摘要： An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

摘要翻译： 提供了一种设备，存储器件控制器和控制存储器件的方法。 该示例设备可以包括坏块位图参考单元，其被配置为基于给定的存储器地址从坏块位图获得坏块信息，给定存储器地址是与逻辑存储器对应的逻辑存储器地址之一和物理存储器地址 指示与给定存储器地址相对应的给定存储块是否为坏块的坏块信息和被配置为获得与逻辑存储器地址对应的物理存储器地址的存储器映射单元，并且被配置为获得预留的物理存储器地址 对应于物理存储器地址，如果坏块信息指示给定的存储器块是坏块。 在一个示例中，该装置可以被实现为包括闪存转换层（FTL）的存储器件控制器。

公开(公告)号：US20060004971A1

公开(公告)日：2006-01-05

申请号：US10990065

申请日：2004-11-16

申请人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

发明人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.

公开(公告)号：US07529879B2

公开(公告)日：2009-05-05

申请号：US10990065

申请日：2004-11-16

申请人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

发明人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.

摘要翻译： 提供了控制闪速存储器的存储器系统和方法，其响应于接收到闪速存储器的命令而执行增量合并操作的多个合并级中的一个。 执行多个合并阶段中的一个可以包括：如果闪存正在执行增量合并操作，则向闪存接收命令，确定闪存是否正在执行增量合并操作并执行增量合并操作的下一个合并阶段 。

公开(公告)号：US20070166876A1

公开(公告)日：2007-07-19

申请号：US11324453

申请日：2006-01-03

申请人： Young-Gon Kim ,  David Gibson ,  Michael Warner ,  Philip Damberg ,  Philip Osborn

发明人： Young-Gon Kim ,  David Gibson ,  Michael Warner ,  Philip Damberg ,  Philip Osborn

IPC分类号： H01L21/00

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

摘要： An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

摘要翻译： 具有独立测试和修复功能的超薄系统级封装（SIP）包括：插入器，其布置在其顶表面和底表面上，多个封装的半导体芯片通过焊料凸块安装，根据Land Grid Array （LGA）格式，并且其中在SIP上不使用底部填充物。

公开(公告)号：US20060033216A1

公开(公告)日：2006-02-16

申请号：US11252305

申请日：2005-10-17

申请人： L. Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig Mitchell ,  Wael Zohni ,  Ilyas Mohammed

发明人： L. Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig Mitchell ,  Wael Zohni ,  Ilyas Mohammed

IPC分类号： H01L23/52

CPC分类号： H01L23/528 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/78301 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00014

摘要： A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

摘要翻译： 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，通过形成焊接桥，各个单元的多分支迹线被选择性地连接，以便在连接到不同的芯片选择端子的不同单元中留下芯片的芯片选择触点，从而将这些芯片连接到不同的垂直总线 。 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。

公开(公告)号：US07935569B2

公开(公告)日：2011-05-03

申请号：US11975996

申请日：2007-10-23

申请人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John B. Riley, III

发明人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John B. Riley, III

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

摘要翻译： 包括底部单元半导体芯片的底部单元安装到电路板，并且诸如封装半导体芯片的一个或多个顶部元件安装到底部单元。 可以使用与将组件安装到电路板上通常使用的相同的技术来执行两种安装操作。 通常的封装芯片可以用作顶部元件，从而降低组装成本，并允许通过选择封装的芯片来定制组件。 该组件实现了与使用预组装的堆叠芯片单元获得的效果相似的优点，但是不包含包装在封装芯片中的裸芯片的特殊处理费用。

公开(公告)号：US07335995B2

公开(公告)日：2008-02-26

申请号：US11062413

申请日：2005-02-22

申请人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

发明人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/528 ,  H01L23/66 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/4824 ,  H01L2224/78301 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.

摘要翻译： 提供了一种微电子组件和制造方法，其包括诸如封装的芯片或元件的微电子元件。 多个可表面安装的触点以暴露于微电子元件的主表面的阵列布置。 将一个或多个无源元件（例如电阻器，电感器，电容器或其组合）安装到微电子元件，其中无源元件的内部端子导电地安装到一个触点的暴露表面，并且外部端子垂直移位 从微电子元件的主表面。

公开(公告)号：US07294928B2

公开(公告)日：2007-11-13

申请号：US10656534

申请日：2003-09-05

申请人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John B. Riley

发明人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John B. Riley

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L23/498 ,  H05K1/14

CPC分类号： H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

摘要翻译： 包括底部单元半导体芯片的底部单元安装到电路板，并且诸如封装半导体芯片的一个或多个顶部元件安装到底部单元。 可以使用与将组件安装到电路板上通常使用的相同的技术来执行两种安装操作。 通常的封装芯片可以用作顶部元件，从而降低组装成本，并允许通过选择封装的芯片来定制组件。 该组件实现了与使用预组装的堆叠芯片单元获得的效果相似的优点，但是不包含包装在封装芯片中的裸芯片的特殊处理费用。

公开(公告)号：US20070252247A1

公开(公告)日：2007-11-01

申请号：US11453216

申请日：2006-06-15

申请人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

发明人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

摘要翻译： 半导体封装包括引线结构，其上安装半导体管芯，其中至少一些引线的至少一部分延伸到封装的轴线或轴线处，或跨越封装的轴线或轴线，以阻止封装的热诱导生长， 减小或最小化包装内的应变和与之相关联的可靠性。