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    Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements
    1.
    发明授权
    Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements 有权

    公开(公告)号：US11735521B2

    公开(公告)日：2023-08-22

    申请号：US17510190

    申请日：2021-10-25

    Applicant: Intel Corporation

    Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni ,  Vincent E. Dorgan ,  Uddalak Bhattacharya

    IPC: H10B20/20 ,  H01L23/525 ,  H01L29/78 ,  H01L27/02

    CPC classification number: H01L23/5252 ,  H01L27/0251 ,  H01L29/7833 ,  H10B20/20

    Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

    Hot carrier injection fuse memory
    2.
    发明授权
    Hot carrier injection fuse memory 有权

    公开(公告)号：US11348651B2

    公开(公告)日：2022-05-31

    申请号：US16147119

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Sarvesh Kulkarni ,  Vincent Dorgan ,  Inanc Meric ,  Venkata Krishna Rao Vangara ,  Uddalak Bhattacharya ,  Jeffrey Hicks

    IPC: G11C17/16 ,  G11C17/18

    Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure.

    Metal interconnect fuse memory arrays
    3.
    发明授权
    Metal interconnect fuse memory arrays 有权

    公开(公告)号：US11239149B2

    公开(公告)日：2022-02-01

    申请号：US15942952

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Uddalak Bhattacharya ,  Zhanping Chen ,  Walid Hafez

    IPC: G11C11/00 ,  H01L23/50 ,  H01L21/768 ,  H01L21/77

    Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

    Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements
    4.
    发明授权
    Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements 有权

    公开(公告)号：US11189564B2

    公开(公告)日：2021-11-30

    申请号：US15943541

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni ,  Vincent E. Dorgan ,  Uddalak Bhattacharya

    IPC: H01L23/525 ,  H01L29/78 ,  H01L27/112 ,  H01L27/02

    Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

    DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)
    5.
    发明申请
    DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) 有权
    双端口静态随机存取存储器（SRAM）

    公开(公告)号：US20160078926A1

    公开(公告)日：2016-03-17

    申请号：US14948196

    申请日：2015-11-20

    Applicant: Intel Corporation

    Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

    Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

    Abstract translation: 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

    Dual-port static random access memory (SRAM)
    6.
    发明授权
    Dual-port static random access memory (SRAM) 有权
    双端口静态随机存取存储器（SRAM）

    公开(公告)号：US09208853B2

    公开(公告)日：2015-12-08

    申请号：US13842086

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

    IPC: G11C11/40 ,  G11C11/412 ,  G11C8/16

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

    Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

    Abstract translation: 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

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