公开(公告)号：US09607687B2

公开(公告)日：2017-03-28

申请号：US14948196

申请日：2015-11-20

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

IPC: G11C11/40 ,  G11C11/419 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

公开(公告)号：US10902893B2

公开(公告)日：2021-01-26

申请号：US15809647

申请日：2017-11-10

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

公开(公告)号：US10818326B2

公开(公告)日：2020-10-27

申请号：US15854549

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

公开(公告)号：US20180226109A1

公开(公告)日：2018-08-09

申请号：US15854549

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

公开(公告)号：US20180082722A1

公开(公告)日：2018-03-22

申请号：US15809647

申请日：2017-11-10

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

公开(公告)号：US20160267952A1

公开(公告)日：2016-09-15

申请号：US15162477

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract translation: 负位线写入辅助电路包括被配置为有助于驱动位线的电容的偏置电容器。 负位线写辅助电路可以在电路内模块化复制，以在写操作期间改变位线上的负电压量。 位线写辅助电路可以直接耦合到位线，从而不需要向写驱动器添加下拉晶体管。

公开(公告)号：US10002654B2

公开(公告)日：2018-06-19

申请号：US14752464

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Pramod Kolar ,  Ankit Sharma ,  Subho Chatterjee ,  Karthik Subramanian ,  Farhana Sheikh ,  Wei-Hsiang Ma

IPC: G11C8/08 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

公开(公告)号：US09812189B2

公开(公告)日：2017-11-07

申请号：US14731319

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Wei-Hsiang Ma ,  Gunjan H. Pandya

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

公开(公告)号：US09208853B2

公开(公告)日：2015-12-08

申请号：US13842086

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

IPC: G11C11/40 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract translation: 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

公开(公告)号：US09818460B2

公开(公告)日：2017-11-14

申请号：US15162477

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.