公开(公告)号：US20130309864A1

公开(公告)日：2013-11-21

申请号：US13671583

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim BARTH ,  Mathias VAUPEL ,  Rainer STEINER ,  Werner ROBL ,  Jens POHL ,  Joern PLAGMANN ,  Gottfried BEER

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

公开(公告)号：US20160168739A1

公开(公告)日：2016-06-16

申请号：US14948463

申请日：2015-11-23

Applicant: Infineon Technologies AG

Inventor： Werner ROBL ,  Michael MELZL ,  Manfred SCHNEEGANS ,  Bernhard WEIDGANS ,  Franziska HAERING

IPC: C25D3/40 ,  H01L21/768 ,  C25D5/02 ,  C25D5/50 ,  C25D3/38 ,  C25D3/48 ,  C25D3/46 ,  C25D3/50 ,  C25D3/30 ,  C25D3/12 ,  H01L23/498 ,  C25D7/12

CPC classification number: C25D3/38 ,  C25D3/12 ,  C25D3/32 ,  C25D3/46 ,  C25D3/48 ,  C25D3/52 ,  C25D5/50 ,  C25D7/123 ,  C25D15/00 ,  H01L21/2885 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450° C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.

Abstract translation: 可以提供电解质。 电解质可以包括至少一种配置成在高于约100℃的温度下分解或蒸发的添加剂和水溶性金属盐，并且电解质可以不含碳纳米管。 在各种实施方案中，可以提供形成金属层的方法：该方法可以包括使用电解质在载体上沉积金属层，其中电解质可以包括至少一种添加剂，其构造成在高于约100℃的温度下分解或蒸发 ℃和水溶性金属盐，其中电解质不含碳纳米管; 并退火金属层以形成包含多个孔的金属层。 在各种实施例中，可以提供半导体器件。 半导体器件可以包括包括多个孔的金属层，其中多个孔可以形成在金属层中，作为存在于多个孔中并具有至少部分分解或蒸发的添加剂的残留物。 为了在较宽的温度范围（高达450℃）保持高弹性，粘合层可以稳定金属晶界，并且可以固定在金属颗粒内滑动的位错。 在各种实施例中，提供金属层。 金属层可以包括具有椭圆形或球形形状的多个孔。

公开(公告)号：US20250057051A1

公开(公告)日：2025-02-13

申请号：US18448657

申请日：2023-08-11

Applicant: Infineon Technologies AG

Inventor： Michael KIRSCH ,  Patrick HANEKAMP ,  Werner ROBL ,  Klemens PRÜGL ,  Juergen ZIMMER ,  Christoph OSWALD

IPC: H10N50/85 ,  C23C14/16 ,  C23C14/34 ,  C23C28/02 ,  C25D3/56 ,  C25D5/02 ,  C25D7/12 ,  G01R33/02 ,  H10N50/01 ,  H10N59/00

Abstract: A layered structure includes a silicon-based substrate comprising a substrate surface; a titanium-copper seed layer arranged on the substrate surface, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface such that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is arranged directly on the titanium layer, such that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer arranged directly on the copper layer of the titanium-copper seed layer such that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer.

公开(公告)号：US20190221533A1

公开(公告)日：2019-07-18

申请号：US16246912

申请日：2019-01-14

Applicant: Infineon Technologies AG

Inventor： Horst THEUSS ,  Rudolf BERGER ,  Walter HARTNER ,  Veronika HUBER ,  Werner ROBL

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/05 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/3512

Abstract: A semiconductor device includes a semiconductor chip, an electrical connection element for electrically connecting the semiconductor device to a carrier, and a metallization adjoining the electrical connection element, the metallization contains porous nanocrystalline copper that contains portions of organic acids.

公开(公告)号：US20130062770A1

公开(公告)日：2013-03-14

申请号：US13671573

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim BARTH ,  Mathias VAUPEL ,  Rainer STEINER ,  Werner ROBL ,  Jens POHL ,  Joern PLAGMANN ,  Gottfried BEER

IPC: H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract translation: 一个或多个实施例涉及半导体结构，包括：覆盖工件表面的阻挡层; 覆盖阻挡层的种子层; 覆盖所述种子层的抑制剂层，所述抑制剂层具有暴露所述种子层的一部分的开口以及覆盖所述种子层的暴露部分的填充层。