公开(公告)号：US20160240366A1

公开(公告)日：2016-08-18

申请号：US14624205

申请日：2015-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Engelhardt ,  Hannes Eder

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/66 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/304 ,  H01L21/67103 ,  H01L21/67248 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of thinning a wafer includes thinning the wafer using a grinding process. The wafer, after the grinding processing, has a first non-uniformity in thickness. The thinned wafer is etched using a plasma process. The wafer after the etching processing has a second non-uniformity in thickness. The second non-uniformity is less than the first non-uniformity.

Abstract translation: 削薄晶片的方法包括使用研磨工艺来稀薄晶片。 在研磨处理之后，晶片具有第一不均匀的厚度。 使用等离子体工艺蚀刻薄的晶片。 蚀刻处理后的晶片具有第二厚度不均匀性。 第二个不均匀度小于第一个不均匀性。

公开(公告)号：US09275916B2

公开(公告)日：2016-03-01

申请号：US13886283

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/784 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。

公开(公告)号：US20150108666A1

公开(公告)日：2015-04-23

申请号：US14058213

申请日：2013-10-18

Applicant: Infineon Technologies AG

Inventor： Manfred ENGELHARDT ,  Edward Fuergut ,  Hannes Eder

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Abstract translation: 一种形成薄化的封装芯片结构的方法，其中所述方法包括提供布置在电子芯片内的分离结构，通过封装结构封装电子芯片的一部分，并且选择性地稀释由封装结构部分封装的电子芯片，使得 封装结构的厚度比薄的电子芯片保持更大的厚度，其中分离结构用作减薄停止。

公开(公告)号：US09627287B2

公开(公告)日：2017-04-18

申请号：US14058213

申请日：2013-10-18

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Edward Fuergut ,  Hannes Eder

IPC: H01L21/762 ,  H01L23/28 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

公开(公告)号：US09576875B2

公开(公告)日：2017-02-21

申请号：US14591014

申请日：2015-01-07

Applicant: Infineon Technologies AG

Inventor： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

IPC: H01L23/31 ,  H01L23/485 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract translation: 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US20140327003A1

公开(公告)日：2014-11-06

申请号：US13886283

申请日：2013-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward FUERGUT ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。