Invention Grant
US09576875B2 Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
有权
用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
- Patent Title: Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
- Patent Title (中): 用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
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Application No.: US14591014Application Date: 2015-01-07
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Publication No.: US09576875B2Publication Date: 2017-02-21
- Inventor: Reinhard Hess , Katharina Umminger , Gabriel Maier , Markus Menath , Gunther Mackh , Hannes Eder , Alexander Heinrich
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee Address: DE Neubiberg
- Agency: Viering, Jentschura & Partner mbB
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/485 ; H01L21/78 ; H01L21/3065 ; H01L21/56 ; H01L23/00 ; H01L21/683 ; H01L21/02 ; H01L21/768
Abstract:
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
Public/Granted literature
Information query
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