公开(公告)号：US20210265488A1

公开(公告)日：2021-08-26

申请号：US16797097

申请日：2020-02-21

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Alexander Reznicek ,  Veeraraghavan Basker ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/223

Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

公开(公告)号：US11024536B2

公开(公告)日：2021-06-01

申请号：US16387687

申请日：2019-04-18

Applicant: International Business Machines Corporation

Inventor： Adra Carr ,  Vimal Kamineni ,  Ruilong Xie ,  Andrew Greene ,  Nigel Cave ,  Veeraraghavan Basker

IPC: H01L21/768

Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.

公开(公告)号：US09627278B2

公开(公告)日：2017-04-18

申请号：US14741418

申请日：2015-06-16

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L29/45

CPC classification number: H01L21/845 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/456

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.

公开(公告)号：US09559014B1

公开(公告)日：2017-01-31

申请号：US14950583

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31051 ,  H01L21/31056 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

Abstract translation: 一种技术涉及形成自对准场效应晶体管。 一种起动穿孔止动器，包括一个其上形成有多个翅片的基片，一个n型场效应晶体管（NFET）区，一个p型场效应晶体管（PFET）区，以及一个具有边界缺陷的中心区 首先提供NFET区域和PFET区域的界面。 然后对场效应晶体管进行掩模以掩蔽NFET区域和PFET区域，使得中心区域被暴露。 然后通过蚀刻中心区域形成中心边界区域以去除边界缺陷。

公开(公告)号：US09337254B1

公开(公告)日：2016-05-10

申请号：US14950141

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8242 ,  H01L49/02 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/8239

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/8239 ,  H01L27/10826 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/945

Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.

公开(公告)号：US11349001B2

公开(公告)日：2022-05-31

申请号：US16598065

申请日：2019-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan Basker ,  Juntao Li

IPC: H01L21/8238 ,  H01L27/11 ,  H01L29/417 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

公开(公告)号：US20220130980A1

公开(公告)日：2022-04-28

申请号：US17569669

申请日：2022-01-06

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Alexander Reznicek ,  Veeraraghavan Basker ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/223 ,  H01L29/06

Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

公开(公告)号：US20180047637A1

公开(公告)日：2018-02-15

申请号：US15795370

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L29/167 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/02

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

公开(公告)号：US09805987B2

公开(公告)日：2017-10-31

申请号：US14845448

申请日：2015-09-04

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/10 ,  H01L27/092 ,  H01L21/3065

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31051 ,  H01L21/31056 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

公开(公告)号：US11887890B2

公开(公告)日：2024-01-30

申请号：US17553950

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/28141 ,  H01L21/31111 ,  H01L21/76834 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/785

Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.