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    NEURAL NETWORK OPERATION SYSTEM
    2.
    发明申请
    NEURAL NETWORK OPERATION SYSTEM 有权

    公开(公告)号：US20220172035A1

    公开(公告)日：2022-06-02

    申请号：US17310203

    申请日：2019-01-28

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Xiaoxin XU ,  Qing LUO ,  Ming LIU

    IPC: G06N3/063 ,  H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  G11C11/54

    Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

    SELECTION DEVICE FOR USE IN BIPOLAR RESISTIVE MEMORY AND MANUFACTURING METHOD THEREFOR
    4.
    发明申请
    SELECTION DEVICE FOR USE IN BIPOLAR RESISTIVE MEMORY AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20190115529A1

    公开(公告)日：2019-04-18

    申请号：US16085400

    申请日：2016-03-18

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Ming LIU ,  Qing LUO ,  Xiaoxin XU ,  Hangbing LV ,  Shibing LONG ,  Qi LIU

    IPC: H01L45/00 ,  H01L27/24 ,  H01L29/51 ,  G11C11/56

    Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.

    MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIASING METHOD
    5.
    发明公开
    MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIASING METHOD 审中-公开

    公开(公告)号：US20230197152A1

    公开(公告)日：2023-06-22

    申请号：US17996194

    申请日：2020-04-14

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Jianguo YANG ,  Xiaoxin XU ,  Ming LIU

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79

    Abstract: Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.

    WRITING METHOD AND ERASING METHOD OF FUSION MEMORY
    6.
    发明申请
    WRITING METHOD AND ERASING METHOD OF FUSION MEMORY 有权

    公开(公告)号：US20220115052A1

    公开(公告)日：2022-04-14

    申请号：US17426053

    申请日：2019-01-28

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Tiancheng GONG ,  Ming LIU

    IPC: G11C11/22 ,  G11C16/14 ,  G11C16/34

    Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

    SELECTOR BASED ON TRANSITION METAL OXIDE AND PREPARATION METHOD THEREFOR
    7.
    发明申请
    SELECTOR BASED ON TRANSITION METAL OXIDE AND PREPARATION METHOD THEREFOR 审中-公开

    公开(公告)号：US20200058704A1

    公开(公告)日：2020-02-20

    申请号：US16486614

    申请日：2017-02-22

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Shibing LONG ,  Qi LIU ,  Ming LIU

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration. In addition, the selector for the resistive random access memory of the present invention has advantages of a simple structure, easy for integration, a low cost, a good uniformity, and compatibility with a CMOS process.

    METHOD FOR PREPARING RESERVOIR ELEMENT
    8.
    发明公开
    METHOD FOR PREPARING RESERVOIR ELEMENT 审中-公开

    公开(公告)号：US20240260488A1

    公开(公告)日：2024-08-01

    申请号：US18559755

    申请日：2022-03-15

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Xiaoxin XU ,  Wenxuan SUN ,  Jie YU ,  Jinru LAI ,  Xu ZHENG ,  Danian DONG

    IPC: H10N70/00 ,  H10N70/20

    CPC classification number: H10N70/041 ,  H10N70/023 ,  H10N70/026 ,  H10N70/25 ,  H10N70/8836

    Abstract: A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

    MEMORY
    10.
    发明申请
    MEMORY 有权

    公开(公告)号：US20220122997A1

    公开(公告)日：2022-04-21

    申请号：US17310282

    申请日：2019-01-28

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Tiancheng GONG ,  Ming LIU

    IPC: H01L27/1159 ,  H01L27/11597 ,  H01L25/065

    Abstract: Disclosed is a memory, including a plurality of memory units, wherein each memory unit includes: a bulk substrate; a source electrode, a drain electrode and a channel region extending between a source region and a drain region that are located on the bulk substrate; a deep-level defect dielectric layer on the channel region; and a gate electrode on the deep-level defect dielectric layer. The memory of the present disclosure allows the memory unit to operate in the charge trapping mode and the polarization inversion mode. Therefore, the memory has functions of both DRAM and NAND, and combines the advantages of the two.

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