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    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    2.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20160005969A1

    公开(公告)日：2016-01-07

    申请号：US14857217

    申请日：2015-09-17

    申请人： Hitachi, Ltd.

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    3.
    发明授权
    Nonvolatile semiconductor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US09070621B2

    公开(公告)日：2015-06-30

    申请号：US14076261

    申请日：2013-11-10

    申请人： Hitachi, Ltd.

    发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

    IPC分类号： H01L27/24 ,  H01L27/102

    CPC分类号： H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

    摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

    摘要翻译： 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶界。

    Data processing method, edge device, and data processing system
    5.
    发明授权
    Data processing method, edge device, and data processing system 有权

    公开(公告)号：US11323344B2

    公开(公告)日：2022-05-03

    申请号：US17355251

    申请日：2021-06-23

    申请人： HITACHI, LTD.

    发明人： Kenichi Shimbo ,  Tadanobu Toba ,  Masaharu Kinoshita

    IPC分类号： H04L1/18 ,  H04L1/00 ,  H04L29/08 ,  H04L67/12 ,  H04L43/08 ,  G16Y30/10 ,  H04N13/194 ,  H04N13/106 ,  G06F12/00 ,  G06F15/167

    摘要： A data processing method is performed by an edge device acquiring collected data from a collection target and a first computer capable of communicating with the edge device. The method includes: a first calculation process of, by the edge device, storing the collected data in a secure region to which referring of internally stored information from outside is not allowable and calculating first data which has a data amount less than the collected data and is irreversible in the secure region based on the stored collected data; a first communication process of, by the edge device, transmitting the first data calculated through the first calculation process to the first computer; and a second calculation process of, by the first computer, calculating second data based on the first data transmitted from the edge device through the first communication process.

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    6.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20140361241A1

    公开(公告)日：2014-12-11

    申请号：US14468513

    申请日：2014-08-26

    申请人： Hitachi, Ltd.

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    PHASE CHANGE MEMORY
    7.
    发明申请
    PHASE CHANGE MEMORY 有权
    相变记忆

    公开(公告)号：US20140151622A1

    公开(公告)日：2014-06-05

    申请号：US14091487

    申请日：2013-11-27

    申请人： Hitachi, Ltd.

    发明人： Takasumi Oyanagi ,  Norikatsu Takaura ,  Mitsuharu Tai ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Kenichi Akita ,  Masahito Kitamura

    IPC分类号： H01L45/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1675

    摘要： A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.

    摘要翻译： 提供能够增加低电阻状态下的电阻的超晶格相变存储器。 相变存储器包括第一电极，设置在第一电极上的第二电极和在第一电极和第二电极之间具有超晶格结构的相变存储层，超晶格结构包括重复形成的Sb 2 Te 3和GeTe层。 具有超晶格结构的相变存储层包括含有与第一电极接触的Zr的Sb2Te3层。

    Semiconductor storage device and method for manufacturing same
    10.
    发明授权
    Semiconductor storage device and method for manufacturing same 有权
    半导体存储装置及其制造方法

    公开(公告)号：US09153775B2

    公开(公告)日：2015-10-06

    申请号：US14468513

    申请日：2014-08-26

    申请人： Hitachi, Ltd.

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  H01L27/22

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。