公开(公告)号：US09490429B2

公开(公告)日：2016-11-08

申请号：US14860349

申请日：2015-09-21

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Akio Shima ,  Kenzo Kurotsuchi ,  Takashi Kobayashi

IPC: H01L45/00 ,  H01L27/06 ,  H01L27/102 ,  H01L29/792 ,  H01L27/24 ,  H01L27/115 ,  G11C13/00

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

公开(公告)号：US09070621B2

公开(公告)日：2015-06-30

申请号：US14076261

申请日：2013-11-10

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

IPC: H01L27/24 ,  H01L27/102

CPC classification number: H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

Abstract translation: 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶界。

公开(公告)号：US09024284B2

公开(公告)日：2015-05-05

申请号：US14091487

申请日：2013-11-27

Applicant: Hitachi, Ltd.

Inventor： Takasumi Oyanagi ,  Norikatsu Takaura ,  Mitsuharu Tai ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Kenichi Akita ,  Masahito Kitamura

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1675

Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.

Abstract translation: 提供能够增加低电阻状态下的电阻的超晶格相变存储器。 相变存储器包括第一电极，设置在第一电极上的第二电极和在第一电极和第二电极之间具有超晶格结构的相变存储层，超晶格结构包括重复形成的Sb 2 Te 3和GeTe层。 具有超晶格结构的相变存储层包括含有与第一电极接触的Zr的Sb2Te3层。

公开(公告)号：US11423299B2

公开(公告)日：2022-08-23

申请号：US16204461

申请日：2018-11-29

Applicant: Hitachi, Ltd.

Inventor： Tadashi Okumura ,  Mitsuharu Tai ,  Masahiko Ando ,  Sanato Nagata ,  Norifumi Kameshiro

IPC: G06N3/08 ,  G02F1/21

Abstract: A device includes an input unit, a nonlinear converter, and an output unit. The nonlinear converter and the output unit are connected via a connection path having a delay mechanism that realizes a feedback loop giving a delay to a signal. The delay mechanism includes a conversion mechanism that generates a plurality of signals with different delay times using the signal output from the nonlinear converter, generates a new signal by superimposing the plurality of signals, and outputs the generated signal to the output unit.

公开(公告)号：US10338046B2

公开(公告)日：2019-07-02

申请号：US15760777

申请日：2016-01-15

Applicant: HITACHI, LTD.

Inventor： Masahiko Ando ,  Sanato Nagata ,  Shirun Ho ,  Yuji Suwa ,  Mitsuharu Tai ,  Kenzo Kurotsuchi ,  Hiromasa Takahashi ,  Norifumi Kameshiro ,  Seiichi Suzuki

IPC: C12M1/34 ,  G01N27/27 ,  G01N33/00 ,  G01N27/414

Abstract: An object of the present invention is to provide an artificial olfactory sensing system capable of sniffing out various odors highly sensitively.The artificial olfactory sensing system includes: plural sensor cells on a lipid membrane of each of which olfactory receptors have developed; and plural ion-sensitive field-effect transistors (ISFETs) that correspondingly exist to the sensor cells on a one-on-one basis. A response signal showing that each of the olfactory receptors of each of the sensor cells has recognized an odor molecule is converted into an electric signal by an ISFET corresponding to each of the sensor cells.

公开(公告)号：US20140151622A1

公开(公告)日：2014-06-05

申请号：US14091487

申请日：2013-11-27

Applicant: Hitachi, Ltd.

Inventor： Takasumi Oyanagi ,  Norikatsu Takaura ,  Mitsuharu Tai ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Kenichi Akita ,  Masahito Kitamura

IPC: H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1675

Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.

Abstract translation: 提供能够增加低电阻状态下的电阻的超晶格相变存储器。 相变存储器包括第一电极，设置在第一电极上的第二电极和在第一电极和第二电极之间具有超晶格结构的相变存储层，超晶格结构包括重复形成的Sb 2 Te 3和GeTe层。 具有超晶格结构的相变存储层包括含有与第一电极接触的Zr的Sb2Te3层。