公开(公告)号：US10522747B2

公开(公告)日：2019-12-31

申请号：US16278766

申请日：2019-02-19

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Po-Kang Wang

IPC: H01L43/08 ,  H01F10/30 ,  H01F10/32 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/16

Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

公开(公告)号：US20190189911A1

公开(公告)日：2019-06-20

申请号：US16278766

申请日：2019-02-19

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Po-Kang Wang

IPC: H01L43/08 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01F10/30 ,  H01F10/16

Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

公开(公告)号：US20180269387A1

公开(公告)日：2018-09-20

申请号：US15972284

申请日：2018-05-07

Applicant: Headway Technologies, Inc.

Inventor： Jodi Mari Iwata ,  Guenole Jan ,  Ru-Ying Tong ,  Po-Kang Wang

IPC: H01L43/10 ,  H01F41/32 ,  H01F10/32 ,  H01F10/16 ,  H01L43/12 ,  H01L43/08 ,  H01F10/14

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/142 ,  H01F10/16 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/32 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al. Methods are also provided for forming composite free layers where interfacial perpendicular anisotropy is generated therein by contact of the free layer with oxidized materials.

公开(公告)号：US09966529B1

公开(公告)日：2018-05-08

申请号：US15461779

申请日：2017-03-17

Applicant: Headway Technologies, Inc.

Inventor： Jodi Mari Iwata ,  Guenole Jan ,  Ru-Ying Tong ,  Po-Kang Wang

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/14 ,  H01F10/16 ,  H01F10/32 ,  H01F41/32

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3286 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, metal clusters are formed in the FL and are subsequently partially or fully oxidized by scavenging oxygen to generate additional FL/oxide interfaces that enhance PMA, provide an acceptable resistance x area (RA) value, and preserve the magnetoresistive ratio. In other embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al.

公开(公告)号：US09842988B2

公开(公告)日：2017-12-12

申请号：US14803111

申请日：2015-07-20

Applicant: Headway Technologies, Inc.

Inventor： Huanlong Liu ,  Yuan-Jen Lee ,  Jian Zhu ,  Guenole Jan ,  Po-Kang Wang

IPC: H01L29/82 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01F41/30 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.

公开(公告)号：US09361923B1

公开(公告)日：2016-06-07

申请号：US14690609

申请日：2015-04-20

Applicant: Headway Technologies, Inc.

Inventor： Yue Liu ,  Moris Dovek ,  Glen Garfunkel ,  Yaguang Wei ,  Yuhui Tang ,  Po-Kang Wang

IPC: G11B5/127 ,  G11B5/60 ,  G11B5/31 ,  G11B5/11

CPC classification number: G11B5/3116 ,  G11B5/11 ,  G11B5/3163

Abstract: A shield structure for a PMR writer is disclosed and features a first trailing shield on a write gap, and a second (PP3) trailing shield on the first trailing shield and magnetically connected to the main pole layer. From a top-down view along the down-track direction, the PP3 trailing shield has various shapes to provide shape anisotropy such that following hard magnet or reverse magnet initialization, PP3 trailing shield magnetic orientation has a stable three domain configuration thereby minimizing skip track erasure (STE) or improving area density capability (ADC). At least one sloped side is introduced that forms an angle >90 degrees with the PP3 trailing shield backside. In other embodiments, a thinner leading shield may be used to improve STE. The PP3 trailing shield may have a dome shape or a planar shape from a down-track cross-sectional view.

Abstract translation: 公开了一种用于PMR写入器的屏蔽结构，其特征在于写间隙上的第一尾部屏蔽和在第一后屏蔽上的第二（PP3）后屏蔽，并且磁连接到主极层。 PP3后挡板沿着向下的方向从上向下看具有各种形状，以提供形状各向异性，使得随后的硬磁体或反磁体初始化，PP3后屏蔽磁方向具有稳定的三域结构，从而最小化跳过轨迹擦除 （STE）或改善面积密度能力（ADC）。 引入至少一个倾斜的侧面，与PP3后挡板背面形成> 90度的角度。 在其他实施例中，可以使用更薄的前导屏蔽来改善STE。 PP3后挡板可以具有从下轨道横截面视图的圆顶形状或平面形状。

公开(公告)号：US08970985B2

公开(公告)日：2015-03-03

申请号：US14139069

申请日：2013-12-23

Applicant: Headway Technologies, Inc.

Inventor： Lijie Guan ,  Po-Kang Wang ,  Moris Dovek ,  Joe Smyth ,  Kenichi Takano ,  Yoshitaka Sasaki

IPC: G11B5/23 ,  G11B5/31 ,  G11B5/127

CPC classification number: G11B5/1278 ,  G11B5/232 ,  G11B5/3116 ,  G11B5/3146

Abstract: A structure and a process for a perpendicular write pole that provides increased magnetic flux at the ABS is disclosed. This is accomplished by increasing the amount of write flux that originates above the write gap, without changing the pole taper at the ABS. Three embodiment of the invention are discussed.

公开(公告)号：US20180358071A1

公开(公告)日：2018-12-13

申请号：US15616116

申请日：2017-06-07

Applicant: Headway Technologies, Inc.

Inventor： Huanlong Liu ,  Guenole Jan ,  Yuan-Jen Lee ,  Jian Zhu ,  Po-Kang Wang

IPC: G11C11/16

Abstract: Circuits and methods for programming a MTJ stack of an MRAM cell minimizes a ferromagnetic free layer or pinned layer polarization reversal due to back-hopping. The programming begins by applying a first segment of the segment of the write pulse at a first write voltage level for a first time period to program the MTJ stack. A second segment of the segment of the write pulse at a second write voltage level that is less than the first write voltage level is applied to the magnetic tunnel junction stack for a second time period to correct the polarization of the MTJ when the MTJ stack has reversed polarization during the first time period. The second segment of the segment of the write pulse may be a ramp, or multiple ramps, or have a quiescent period between it and the first segment of the write pulse.

公开(公告)号：US09805816B2

公开(公告)日：2017-10-31

申请号：US15078182

申请日：2016-03-23

Applicant: Headway Technologies, Inc.

Inventor： Guenole Jan ,  Po-Kang Wang ,  Yuan-Jen Lee ,  Jian Zhu ,  Huanlong Liu

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/16 ,  G11C11/409 ,  G11C11/419 ,  G11C17/02 ,  H01L43/12 ,  G11C17/16 ,  H01L27/22

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/409 ,  G11C11/419 ,  G11C17/02 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/228 ,  H01L43/12

Abstract: An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

公开(公告)号：US09070383B2

公开(公告)日：2015-06-30

申请号：US14139091

申请日：2013-12-23

Applicant: Headway Technologies, Inc.

Inventor： Lijie Guan ,  Po-Kang Wang ,  Moris Dovek ,  Joe Smyth ,  Kenichi Takano ,  Yoshitaka Sasaki

IPC: G11B5/23 ,  G11B5/31 ,  G11B5/127

CPC classification number: G11B5/1278 ,  G11B5/232 ,  G11B5/3116 ,  G11B5/3146

Abstract: A structure and a process for a perpendicular write pole that provides increased magnetic flux at the ABS is disclosed. This is accomplished by increasing the amount of write flux that originates above the write gap, without changing the pole taper at the ABS. Three embodiment of the invention are discussed.