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    Self aligned method of forming a semiconductor array of non-volatile memory cells
    1.
    发明授权
    Self aligned method of forming a semiconductor array of non-volatile memory cells 有权
    形成非易失性存储单元的半导体阵列的自对准方法

    公开(公告)号：US06706592B2

    公开(公告)日：2004-03-16

    申请号：US10146569

    申请日：2002-05-14

    Applicant: Geeng-Chuan Michael Chern ,  Chien-Sheng Su

    Inventor： Geeng-Chuan Michael Chern ,  Chien-Sheng Su

    IPC: H01L21336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/66545

    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in trenches using a first layer of conducting material at the bottom of the trenches, and a second layer of conducting material along sidewalls of the trenches. An etch process is used to etch away portions of the first and second layers of the conductive material to form floating gate blocks of the conductive material having sloping portions that terminate in pointed edges formed along the trench sidewalls. The sharpness of the pointed edges are enhanced by the presence of the conductive material disposed along the trench sidewalls.

    Abstract translation: 一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，该半导体衬底在衬底上具有多个间隔开的隔离区域和在衬底上彼此基本上平行的有源区域。 在沟槽底部使用第一层导电材料形成浮动栅极，并沿着沟槽的侧壁形成第二层导电材料。 蚀刻工艺用于蚀刻掉导电材料的第一和第二层的部分，以形成具有沿着沟槽侧壁形成的尖锐边缘终止的倾斜部分的导电材料的浮动栅极块。 通过沿着沟槽侧壁设置的导电材料的存在来增强尖锐边缘的锐度。

    Method Of Making High-Voltage MOS Transistors With Thin Poly Gate
    2.
    发明申请
    Method Of Making High-Voltage MOS Transistors With Thin Poly Gate 审中-公开
    制造具有薄多孔栅极的高压MOS晶体管的方法

    公开(公告)号：US20140273387A1

    公开(公告)日：2014-09-18

    申请号：US13839533

    申请日：2013-03-15

    Applicant: Chien-Sheng Su ,  Jeng-Wei Yang ,  Mandana Tadayoni ,  Yueh-Hsin Chen

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Mandana Tadayoni ,  Yueh-Hsin Chen

    IPC: H01L29/66

    CPC classification number: H01L29/66477 ,  H01L29/66545 ,  H01L29/6659

    Abstract: A method of forming an MOS transistor by forming a poly gate over and insulated from a substrate, forming a layer of protective insulation material on the poly gate, and then performing a first implant of dopant material into portions of the substrate adjacent the poly gate, wherein the layer of protective insulation material and the poly gate block most or all of the first implant from reaching a portion of the substrate underneath the poly gate. One or more spacers are then formed adjacent the poly gate, followed by a second implant of dopant material into portions of the substrate adjacent to the one or more spacers.

    Abstract translation: 一种形成MOS晶体管的方法，该方法是在多晶硅栅极上形成保护绝缘材料层，然后在邻近多晶硅栅极的基板的第一部分中进行第一次掺杂， 其中所述保护绝缘材料层和所述多晶硅栅极阻挡所述第一注入的大部分或全部到达所述多晶硅栅极下方的所述衬底的一部分。 然后在多晶硅栅极附近形成一个或多个间隔物，随后将掺杂剂材料第二次注入到与该一个或多个间隔物相邻的衬底的部分中。

    Non-volatile memory cell having a high K dielectric and metal gate
    4.
    发明授权
    Non-volatile memory cell having a high K dielectric and metal gate 有权
    具有高K电介质和金属栅极的非易失性存储单元

    公开(公告)号：US08883592B2

    公开(公告)日：2014-11-11

    申请号：US13559329

    申请日：2012-07-26

    Applicant: Alexander Kotov ,  Chien-Sheng Su

    Inventor： Alexander Kotov ,  Chien-Sheng Su

    IPC: H01L21/336 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

    Abstract: A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

    Abstract translation: 一种非易失性存储器，包括第一导电类型的衬底，其中形成有第二和第二间隔开的区域，第二导电类型在其间具有沟道区域。 多晶硅金属栅极字线被定位在沟道区的第一部分上方并且通过高K电介质层与其隔开。 字线的金属部分紧邻高K电介质层。 多晶硅浮栅直接与字线相邻并且与字线间隔开，并位于沟道区的另一部分之上并与其绝缘。 多晶硅耦合栅极位于浮栅上并与浮栅隔绝。 多晶硅擦除栅极位于浮动栅极的另一侧并且与浮栅绝缘，位于第二区域的上方并与第二区域绝缘，并且紧邻耦合栅极的另一侧，但与其隔开。

    Method of erasing a flash EEPROM memory
    6.
    发明授权
    Method of erasing a flash EEPROM memory 失效
    擦除闪存EEPROM存储器的方法

    公开(公告)号：US5790460A

    公开(公告)日：1998-08-04

    申请号：US854619

    申请日：1997-05-12

    Applicant: Chih-Liang Chen ,  I-Chuin Peter Chan ,  James C. Yu ,  Chien-Sheng Su ,  Chao-Ven Kao

    Inventor： Chih-Liang Chen ,  I-Chuin Peter Chan ,  James C. Yu ,  Chien-Sheng Su ,  Chao-Ven Kao

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/00

    CPC classification number: G11C16/14

    Abstract: The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.

    Abstract translation: 本发明是擦除闪存EEPROM存储器件的新颖的擦除方法。 这种存储器件的存储单元具有形成在相反导电类型的第二区域中的一种导电类型的第一半导体区域，形成在第一半导体区域中的相反导电类型的源极和漏极区域以及栅极。 第二区域形成在一种导电类型的衬底内。 栅极包括控制栅极和浮置栅极，其保持电荷并覆盖第一半导体区域。 本发明的擦除方法包括以下步骤：将一个极性的第一电压施加到源区和第一和第二半导体区; 并且同时向栅极施加相反极性的第二电压，由此浮置栅极上的任何电荷通过浮置栅极电介质隧穿到第一区域和源极区域中，从而去除由浮动栅极保留的任何电荷。

    Method of forming a memory cell by reducing diffusion of dopants under a gate
    7.
    发明授权
    Method of forming a memory cell by reducing diffusion of dopants under a gate 有权
    通过减少栅极下掺杂剂的扩散形成存储单元的方法

    公开(公告)号：US08785307B2

    公开(公告)日：2014-07-22

    申请号：US13593448

    申请日：2012-08-23

    Applicant: Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    Inventor： Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L21/04

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

    Abstract translation: 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。

    Method of achieving narrow V.sub.T distribution after erase in flash EEPROM
    10.
    发明授权
    Method of achieving narrow V.sub.T distribution after erase in flash EEPROM 失效
    在闪存EEPROM中擦除后实现窄VT分布的方法

    公开(公告)号：US6023426A

    公开(公告)日：2000-02-08

    申请号：US36971

    申请日：1998-03-09

    Applicant: Yuan Tang ,  James C. Yu ,  Chien-Sheng Su

    Inventor： Yuan Tang ,  James C. Yu ,  Chien-Sheng Su

    IPC: G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/3409 ,  G11C16/3404

    Abstract: There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.

    Abstract translation: 提供了一种在擦除之后校正闪存EEPROM存储单元中的过度存储单元的方法，以产生窄的阈值电压分布宽度。 将地电势施加到存储器单元阵列中的所有单元的源和衬底。 第一正脉冲电压以字线为单位，以字线的第一定时序列同时施加到每个字线。 当第一正脉冲电压被施加到第一字线时，第二正时脉冲电压以位线为单位的第二定时序列同时施加到每个位线，然后对于每个后续字线重复，直到 最后一个字线被应用。

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