公开(公告)号：US06169693A

公开(公告)日：2001-01-02

申请号：US09429239

申请日：1999-10-28

Applicant: I-Chuin Peter Chan ,  Feng Frank Qian ,  Hsingya Arthur Wang

Inventor： I-Chuin Peter Chan ,  Feng Frank Qian ,  Hsingya Arthur Wang

IPC: G11C1604

CPC classification number: G11C16/3409 ,  G11C16/14 ,  G11C16/3404

Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.

Abstract translation: 擦除方法通过在沟道区域中存在横向场的情况下快速切换控制栅极上的偏置来在快闪存储器单元上提供自会聚擦除。 优选地，通过对电池的源极和漏极进行差分偏置来提供横向场，并且控制栅极的偏置变化足够快以在浮动栅极处引起瞬态响应。 在通道区域和浮置栅极之间穿过隧穿氧化物的跨瞬时垂直场引起在通道区域和浮动栅极之间引起适度的热载流子注入。 这种方法是自会聚的，因为除非在阵列步骤期间从浮置栅极去除足够数量的载流子，否则不会发生对浮栅的载流子注入。 由于自会聚效应的大部分是随着控制栅极电压的转变而在其后不久发生的，所以在擦除脉冲结束时需要很少的时间来实现该响应。

公开(公告)号：US6026026A

公开(公告)日：2000-02-15

申请号：US985833

申请日：1997-12-05

Applicant: I-Chuin Peter Chan ,  Feng Frank Qian ,  Hsingya Arthur Wang

Inventor： I-Chuin Peter Chan ,  Feng Frank Qian ,  Hsingya Arthur Wang

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3409 ,  G11C16/14 ,  G11C16/3404

Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.

Abstract translation: 擦除方法通过在沟道区域中存在横向场的情况下快速切换控制栅极上的偏置来在快闪存储器单元上提供自会聚擦除。 优选地，通过对电池的源极和漏极进行差分偏置来提供横向场，并且控制栅极的偏置变化足够快以在浮动栅极处引起瞬态响应。 在通道区域和浮置栅极之间穿过隧穿氧化物的跨瞬时垂直场引起在通道区域和浮动栅极之间引起适度的热载流子注入。 这种方法是自会聚的，因为除非在阵列步骤期间从浮置栅极去除足够数量的载流子，否则不会发生对浮栅的载流子注入。 由于自会聚效应的大部分是随着控制栅极电压的转变而在其后不久发生的，所以在擦除脉冲结束时需要很少的时间来实现该响应。

公开(公告)号：US5790460A

公开(公告)日：1998-08-04

申请号：US854619

申请日：1997-05-12

Applicant: Chih-Liang Chen ,  I-Chuin Peter Chan ,  James C. Yu ,  Chien-Sheng Su ,  Chao-Ven Kao

Inventor： Chih-Liang Chen ,  I-Chuin Peter Chan ,  James C. Yu ,  Chien-Sheng Su ,  Chao-Ven Kao

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/00

CPC classification number: G11C16/14

Abstract: The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.

Abstract translation: 本发明是擦除闪存EEPROM存储器件的新颖的擦除方法。 这种存储器件的存储单元具有形成在相反导电类型的第二区域中的一种导电类型的第一半导体区域，形成在第一半导体区域中的相反导电类型的源极和漏极区域以及栅极。 第二区域形成在一种导电类型的衬底内。 栅极包括控制栅极和浮置栅极，其保持电荷并覆盖第一半导体区域。 本发明的擦除方法包括以下步骤：将一个极性的第一电压施加到源区和第一和第二半导体区; 并且同时向栅极施加相反极性的第二电压，由此浮置栅极上的任何电荷通过浮置栅极电介质隧穿到第一区域和源极区域中，从而去除由浮动栅极保留的任何电荷。