公开(公告)号：US07927994B1

公开(公告)日：2011-04-19

申请号：US12961193

申请日：2010-12-06

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC: H01L21/4763

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract translation: 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20100259979A1

公开(公告)日：2010-10-14

申请号：US12422175

申请日：2009-04-10

Applicant: James Yingbo Jia ,  Douglas Lee ,  Bomy Chen

Inventor： James Yingbo Jia ,  Douglas Lee ,  Bomy Chen

IPC: G11C16/04 ,  G11C7/06

CPC classification number: G11C16/0425 ,  G11C11/5628 ,  G11C16/12 ,  G11C2211/5621

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 具有在所述第一端和所述第二端之间的通道区域，与所述沟道区域的第一部分绝缘且与所述第二区域相邻的浮置栅极，与所述浮置栅极相邻并与其绝缘的第一控制栅极， 沟道区域的第二部分，并且与第一区域相邻，第二控制栅极电容耦合到浮置栅极并且位于浮置栅极上。 将单元编程为多个MLC状态之一的方法包括将电流源施加到第一区域。 向第一控制栅极施加足以使通道区域的第二部分导通的第一电压。 第二电压被施加到第二区域，足以使电子从第一区域流向第二区域。 向第二控制栅极施加足以使沟道区域中的电子注入浮置栅极的第三电压。 第三电压不间断地施加，直到浮动栅极被编程为一个状态。

公开(公告)号：US20090039410A1

公开(公告)日：2009-02-12

申请号：US11834574

申请日：2007-08-06

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC: H01L29/788

CPC classification number: H01L29/42328 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract translation: 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20110076816A1

公开(公告)日：2011-03-31

申请号：US12961193

申请日：2010-12-06

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract translation: 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US07868375B2

公开(公告)日：2011-01-11

申请号：US12618632

申请日：2009-11-13

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien Sheng Su ,  Yaw Wen Hu

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

公开(公告)号：US20110127599A1

公开(公告)日：2011-06-02

申请号：US13023443

申请日：2011-02-08

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC: H01L29/788

CPC classification number: H01L29/42328 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract translation: 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20100054043A1

公开(公告)日：2010-03-04

申请号：US12618632

申请日：2009-11-13

Applicant: Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

Inventor： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC: G11C16/04 ,  H01L21/336 ,  G11C11/34 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract translation: 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US6165918A

公开(公告)日：2000-12-26

申请号：US306654

申请日：1999-05-06

Applicant: James Yingbo Jia ,  Jeong-Yeol Choi

Inventor： James Yingbo Jia ,  Jeong-Yeol Choi

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823462 ,  Y10S438/981

Abstract: Systems and methods are described for fabricating semiconductor gate oxides of different thicknesses. Two methods for forming gate oxides of different thicknesses in conjunction with local oxidation of silicon (LOCOS) are disclosed. Similarly, two methods for forming gate oxides of different thicknesses in conjunction with shallow trench isolation (STI) are disclosed. Techniques that use two poly-silicon sub-layers of substantially equal thickness and techniques that use two poly-silicon sub-layers of substantially unequal thickness are described for both LOCOS and STI. The systems and methods provide advantages because gate uniformity and quality are improved, the processes and resulting devices are cleaner, and there is less degradation of carrier mobility.

Abstract translation: 描述了制造不同厚度的半导体栅极氧化物的系统和方法。 公开了两种形成不同厚度的栅氧化物结合局部氧化硅（LOCOS）的方法。 类似地，公开了与浅沟槽隔离（STI）结合形成不同厚度的栅极氧化物的两种方法。 对于LOCOS和STI都描述了使用基本相等厚度的两个多硅子层和使用基本上不等厚度的两个多晶硅子层的技术的技术。 系统和方法提供了优点，因为栅极均匀性和质量得到改善，工艺和所得到的器件更清洁，载体迁移率降低较少。