公开(公告)号：US20100259979A1

公开(公告)日：2010-10-14

申请号：US12422175

申请日：2009-04-10

Applicant: James Yingbo Jia ,  Douglas Lee ,  Bomy Chen

Inventor： James Yingbo Jia ,  Douglas Lee ,  Bomy Chen

IPC: G11C16/04 ,  G11C7/06

CPC classification number: G11C16/0425 ,  G11C11/5628 ,  G11C16/12 ,  G11C2211/5621

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 具有在所述第一端和所述第二端之间的通道区域，与所述沟道区域的第一部分绝缘且与所述第二区域相邻的浮置栅极，与所述浮置栅极相邻并与其绝缘的第一控制栅极， 沟道区域的第二部分，并且与第一区域相邻，第二控制栅极电容耦合到浮置栅极并且位于浮置栅极上。 将单元编程为多个MLC状态之一的方法包括将电流源施加到第一区域。 向第一控制栅极施加足以使通道区域的第二部分导通的第一电压。 第二电压被施加到第二区域，足以使电子从第一区域流向第二区域。 向第二控制栅极施加足以使沟道区域中的电子注入浮置栅极的第三电压。 第三电压不间断地施加，直到浮动栅极被编程为一个状态。

公开(公告)号：US06756632B1

公开(公告)日：2004-06-29

申请号：US10641609

申请日：2003-08-15

Applicant: Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

Inventor： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

IPC: H01L29788

CPC classification number: H03K19/17748 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/7885 ,  H03K19/1778

Abstract: A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

Abstract translation: 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有位于通道的第一部分上方的浮动栅极的分离栅极型，以及位于通道的第二部分上方的控制栅极，其中电子通过热电子注入机制注入浮置栅极。 非易失性存储单元被来自浮动栅极的电子的作用擦除，通过Fowler-Nordheim隧穿隧道穿过与第二区域相邻的控制栅极。 因此，在编程或擦除期间，不会对第二区域施加高电压。 因此，具有第二区域的非易失性存储单元可以直接连接到MOS晶体管的栅极，其一起形成非易失性可编程开关。

公开(公告)号：US07763492B2

公开(公告)日：2010-07-27

申请号：US11807131

申请日：2007-05-25

Applicant: Bomy Chen

Inventor： Bomy Chen

IPC: H01L21/06

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  Y10S438/90

Abstract: A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed in electrical contact with the first electrode. A second electrode is formed in electrical contact with the phase change memory material. Voids are formed in the insulation material to impede heat from the phase change memory material from conducting away therefrom. The voids are formed in pairs, with either a portion of the phase change memory material or the second electrode disposed between the voids.

Abstract translation: 相变存储器件及其制造方法，其包括形成在绝缘材料中的沟槽，该沟槽具有向内倾斜的沟槽深度的相对的侧壁。 第一电极形成在沟槽中。 相变记忆材料形成为与第一电极电接触。 形成与相变记忆材料电接触的第二电极。 在绝缘材料中形成空隙以阻止相变记忆材料的热量远离导线。 这些空隙成对地形成，其中一部分相变记忆材料或第二电极设置在空隙之间。

公开(公告)号：US07605092B2

公开(公告)日：2009-10-20

申请号：US11772080

申请日：2007-06-29

Applicant: Bomy Chen ,  Long Ching Wang ,  Sychyi Fang

Inventor： Bomy Chen ,  Long Ching Wang ,  Sychyi Fang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5389 ,  H01L28/10 ,  H01L28/91 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract translation: 公开了与半导体制品相关联的系统和方法，包括在衬底上形成第一材料层，在限定第一层中的无源元件的区域内蚀刻沟槽，在沟槽的侧壁上形成金属区域，以及形成电介质区域 聚合物材料在衬底上或衬底中。 此外，示例性方法还可以包括在沟槽的侧壁上形成金属区域的区域，使得这些区域的平面条带部分形成无源元件的导电区域，该无源元件相对于主要平面基本上垂直地排列 底物。 其它示例性实施例可以包括与本文所阐述的创新的一个或多个方面一致的各种物品或方法，包括电容和/或感应方面，基于钛和/或钽的电阻方面，产品，通过工艺，封装和复合材料的产品。

公开(公告)号：US20080131982A1

公开(公告)日：2008-06-05

申请号：US12027916

申请日：2008-02-07

Applicant: Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

Inventor： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC: H01L21/02

CPC classification number: H01L28/20 ,  H01C17/267 ,  H01L22/22

Abstract: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

Abstract translation: 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

公开(公告)号：US20070278471A1

公开(公告)日：2007-12-06

申请号：US11443876

申请日：2006-05-30

Applicant: Bomy Chen ,  Yin Yin Lin

Inventor： Bomy Chen ,  Yin Yin Lin

IPC: H01L29/06

CPC classification number: H01L27/2472 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144

Abstract: A novel chalcogenide material has a bulk composition which has a first material selected from the group of Si and Sn, a second material selected from the group of Sb, and a third material selected from the group of Te. The first material, second material, and third material are in a ratio of (Six or Sny) Sb2 Te5, where x is 1≦x≦5, and y is 0.5≦y≦2.0. The material can be used in a switch device, which includes a dielectric/heater layer having a first surface and a second surface opposite the first surface, and the material having a first surface and a second surface opposite the first surface; with the first surface of the material immediately adjacent to and in contact with the first surface of the dielectric/heater layer. A first electrical contact is on the second surface of the dielectric/heater layer. A second electrical contact is on the second surface of the phase changing chalcogenide material. A third electrical contact is on the second surface of the phase changing chalcogenide material, spaced apart from the second electrical contact. The switching device can be programmed such that the channel length separation between the second electrical contact and the third electrical contact on the phase changing chalcogenide material is changed to represent the desired state to be stored in the device. Finally, an array of the above described non-volatile memory cells can be formed in a dielectric/heater layer and the chalcogenide material.

Abstract translation: 新型硫族化物材料具有本体组合物，其具有选自Si和Sn的第一材料，选自Sb的第二材料和选自Te组的第三材料。 第一材料，第二材料和第三材料的比例为（Si x Si x Si y Sb y Sb 2 Sb 2 O 3） ，其中x是1 <= x <= 5，y是0.5 <= y <= 2.0。 该材料可以用在开关装置中，其包括具有第一表面和与第一表面相对的第二表面的电介质/加热器层，并且该材料具有与第一表面相对的第一表面和第二表面; 其中材料的第一表面紧邻电介质/加热器层的第一表面并与其接触。 电介质/加热器层的第二表面上具有第一电接触。 第二个电触点位于相变硫族化物材料的第二个表面上。 相变硫族化物材料的第二表面上的第三电接触与第二电触点间隔开。 切换装置可以被编程为使得在相变硫属化物材料上的第二电接触和第三电接触之间的通道长度间隔被改变以表示要存储在设备中的期望状态。 最后，可以在电介质/加热器层和硫族化物材料中形成上述非易失性存储单元的阵列。

公开(公告)号：US07245529B2

公开(公告)日：2007-07-17

申请号：US11092227

申请日：2005-03-28

Applicant: Bomy Chen ,  Kevin Gene-Wah Jew

Inventor： Bomy Chen ,  Kevin Gene-Wah Jew

IPC: G11C11/34

CPC classification number: G11C27/005 ,  G11C16/10

Abstract: An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on the floating gate which affects the resistance or the capacitance of the channel from which the floating gate is spaced apart. A particular application of the programmable resistor/capacitor is used in a system whereby the resistance or the capacitance can be change or fine tuned as a result of either drift caused by time or by operating conditions such as temperature. Thus, the temperature of the substrate in which the floating gate memory cell is fabricated can be monitored and the resistance or the capacitance of the floating gate memory cell changed dynamically.

Abstract translation: 集成电路可编程电阻器或可编程电容器具有与固定电阻器或固定电容器串联或并联连接的浮动栅极存储器单元。 可以通过浮动栅极上存储的电荷量来改变浮动栅极存储单元的电阻或电容，影响浮动栅极间隔开的沟道的电阻或电容。 可编程电阻器/电容器的特定应用在系统中使用，由此由于由时间引起的漂移或诸如温度的操作条件导致的电阻或电容可以改变或微调。 因此，可以监视其中制造浮动栅极存储单元的衬底的温度，并且动态地改变浮动栅极存储单元的电阻或电容。

公开(公告)号：US07208376B2

公开(公告)日：2007-04-24

申请号：US11070079

申请日：2005-03-01

Applicant: Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

Inventor： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

IPC: H01L21/8247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

Abstract translation: 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

公开(公告)号：US07180127B2

公开(公告)日：2007-02-20

申请号：US10872052

申请日：2004-06-17

Applicant: Bomy Chen ,  Dana Lee

Inventor： Bomy Chen ,  Dana Lee

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7885

Abstract: A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

Abstract translation: 一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。 浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。 横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。 控制门围绕横向突起形成并与其绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

公开(公告)号：US20060220149A1

公开(公告)日：2006-10-05

申请号：US11092227

申请日：2005-03-28

Applicant: Bomy Chen ,  Kevin Jew

Inventor： Bomy Chen ,  Kevin Jew

IPC: H01L29/76

CPC classification number: G11C27/005 ,  G11C16/10

Abstract: An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on the floating gate which affects the resistance or the capacitance of the channel from which the floating gate is spaced apart. A particular application of the programmable resistor/capacitor is used in a system whereby the resistance or the capacitance can be change or fine tuned as a result of either drift caused by time or by operating conditions such as temperature. Thus, the temperature of the substrate in which the floating gate memory cell is fabricated can be monitored and the resistance or the capacitance of the floating gate memory cell changed dynamically.

Abstract translation: 集成电路可编程电阻器或可编程电容器具有与固定电阻器或固定电容器串联或并联连接的浮动栅极存储器单元。 可以通过浮动栅极上存储的电荷量来改变浮动栅极存储单元的电阻或电容，影响浮动栅极间隔开的沟道的电阻或电容。 可编程电阻器/电容器的特定应用在系统中使用，由此由于由时间引起的漂移或诸如温度的操作条件导致的电阻或电容可以改变或微调。 因此，可以监视其中制造浮动栅极存储单元的衬底的温度，并且动态地改变浮动栅极存储单元的电阻或电容。