公开(公告)号：US06960803B2

公开(公告)日：2005-11-01

申请号：US10693067

申请日：2003-10-23

Applicant: Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

Inventor： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/76

CPC classification number: H01L21/76895

Abstract: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

Abstract translation: 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US5514609A

公开(公告)日：1996-05-07

申请号：US242382

申请日：1994-05-13

Applicant: Min-Liang Chen ,  Ying-Kit Tsui ,  Jau-Nan Kau

Inventor： Min-Liang Chen ,  Ying-Kit Tsui ,  Jau-Nan Kau

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/1126

Abstract: A read only memory semiconductor integrated circuit device includes an improved cell region and a method of manufacture therefor. The improved cell region includes a recessed dielectric region overlying a gate electrode region. Such recessed dielectric region allows for an implanting or coding step to occur after the dielectric layer is applied to the surface of the device. Coding of the ROM device during a latter processing step shortens product turn-around-time. The improved cell also includes an improved method of manufacture. Such method provides for a dielectric layer formed over a gate electrode of a partially completed device. The method further provides etching the upper portion of the dielectric layer overlying the gate electrode to form a recessed region. A step of coding or implanting is then performed to change the device from enhancement mode into depletion mode, thereby providing the ROM code for the designated cell.

Abstract translation: 只读存储器半导体集成电路器件包括改进的单元区域及其制造方法。 改进的单元区域包括覆盖栅极电极区域的凹陷的电介质区域。 这种凹入的介电区域允许在将介电层施加到器件的表面之后发生注入或编码步骤。 在后一处理步骤中ROM设备的编码缩短了产品周转时间。 改进的电池还包括改进的制造方法。 这种方法提供了形成在部分完成的器件的栅电极上的电介质层。 该方法进一步提供蚀刻覆盖栅电极的电介质层的上部以形成凹陷区域。 然后执行编码或植入的步骤，以将设备从增强模式改变为耗尽模式，从而为指定的单元提供ROM代码。

公开(公告)号：US07358559B2

公开(公告)日：2008-04-15

申请号：US11239791

申请日：2005-09-29

Applicant: Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

Inventor： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

Abstract translation: 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

公开(公告)号：US06873006B2

公开(公告)日：2005-03-29

申请号：US10393896

申请日：2003-03-21

Applicant: Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

Inventor： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

Abstract translation: 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

公开(公告)号：US08890225B2

公开(公告)日：2014-11-18

申请号：US13273505

申请日：2011-10-14

Applicant: Ta-Chuan Liao ,  Chien-Kao Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

Inventor： Ta-Chuan Liao ,  Chien-Kao Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

IPC: H01L21/108 ,  H01L21/336 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/1156 ,  H01L21/265 ,  H01L21/28273 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/788 ,  H01L29/7881

Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

Abstract translation: NVM器件包括具有第一区域和第二区域的半导体衬底。 NVM装置包括形成在第一区域中的数据存储结构，并被设计成可操作地保持电荷。 NVM装置包括形成在第二区域中的电容器，并与用于数据操作的数据存储结构耦合。 数据存储结构包括在半导体衬底中的第一类型的第一掺杂阱。 数据存储结构包括第一掺杂阱上的第一栅介质特征。 数据存储结构包括设置在第一栅极电介质特征上并被配置为浮置的第一栅电极。 电容器包括第一类型的第二掺杂阱。 电容器包括第二掺杂阱上的第二栅极电介质特征。 电容器还包括设置在第二栅极电介质特征上并连接到第一栅电极的第二栅电极。

公开(公告)号：US20130092991A1

公开(公告)日：2013-04-18

申请号：US13273505

申请日：2011-10-14

Applicant: Ta-Chuan Liao ,  Chien-Kuo Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

Inventor： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

IPC: H01L27/108 ,  H01L21/336

CPC classification number: H01L27/1156 ,  H01L21/265 ,  H01L21/28273 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/788 ,  H01L29/7881

Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

公开(公告)号：US07749779B2

公开(公告)日：2010-07-06

申请号：US12266443

申请日：2008-11-06

Applicant: Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

Inventor： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC: H01L21/66

CPC classification number: H01L21/76895

Abstract: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

Abstract translation: 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US07208376B2

公开(公告)日：2007-04-24

申请号：US11070079

申请日：2005-03-01

Applicant: Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

Inventor： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

IPC: H01L21/8247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

Abstract translation: 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

公开(公告)号：US5681772A

公开(公告)日：1997-10-28

申请号：US655545

申请日：1996-05-30

Applicant: Min-Liang Chen ,  Ying-Kit Tsui ,  Jau-Nan Kau

Inventor： Min-Liang Chen ,  Ying-Kit Tsui ,  Jau-Nan Kau

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/265

CPC classification number: H01L27/1126

Abstract: A read only memory semiconductor integrated circuit device includes an improved cell region and a method of manufacture therefor. The improved cell region includes a recessed dielectric region overlying a gate electrode region. Such recessed dielectric region allows for an implanting or coding step to occur after the dielectric layer is applied to the surface of the device. Coding of the ROM device during a latter processing step shortens product turn-around-time. The improved cell also includes an improved method of manufacture. Such method provides for a dielectric layer formed over a gate electrode of a partially completed device. The method further provides etching the upper portion of the dielectric layer overlying the gate electrode to form a recessed region. A step of coding or implanting is then performed to change the device from enhancement mode into depletion mode, thereby providing the ROM code for the designated cell.

Abstract translation: 只读存储器半导体集成电路器件包括改进的单元区域及其制造方法。 改进的单元区域包括覆盖栅极电极区域的凹陷的电介质区域。 这种凹入的介电区域允许在将介电层施加到器件的表面之后发生注入或编码步骤。 在后一处理步骤中ROM设备的编码缩短了产品周转时间。 改进的电池还包括改进的制造方法。 这种方法提供了形成在部分完成的器件的栅电极上的电介质层。 该方法进一步提供蚀刻覆盖栅电极的电介质层的上部以形成凹陷区域。 然后执行编码或植入的步骤，以将设备从增强模式改变为耗尽模式，从而为指定的单元提供ROM代码。

公开(公告)号：US08848428B2

公开(公告)日：2014-09-30

申请号：US13548421

申请日：2012-07-13

Applicant: Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

Inventor： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: G11C11/24 ,  H01L27/108 ,  G11C7/00 ,  G11C29/00 ,  H01L29/24

CPC classification number: G11C8/14 ,  G11C11/408 ,  G11C11/4097

Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

Abstract translation: 一个实施例涉及一种包括多个存储单元的存储器件，该多个存储器单元被拼凑在一起以形成存储器阵列。 存储单元包括多个存储单元，其包括设置在半导体衬底上的各自的电容器和相应的晶体管。 电容器包括设置在半导体衬底中的导电区域中的相应的下板。 字线在导电区域上延伸，并且接触将字线连接到导电区域，以将字线耦合到相应电容器的下板。 相应的晶体管被​​布置成使得晶体管的连续栅极被布置在字线的交替侧上。