公开(公告)号：US20100221865A1

公开(公告)日：2010-09-02

申请号：US12780625

申请日：2010-05-14

Applicant: Chung-Wei Chang ,  Han-Chi Liu ,  Chun-Yao Ko ,  Shou-Gwo Wuu

Inventor： Chung-Wei Chang ,  Han-Chi Liu ,  Chun-Yao Ko ,  Shou-Gwo Wuu

IPC: H01L31/18

CPC classification number: H01L27/1463 ,  H01L21/761 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/035272

Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.

Abstract translation: 本公开提供了一种图像传感器半导体器件。 半导体器件包括具有第一类掺杂剂的半导体衬底; 半导体层，其具有不同于所述第一类型掺杂剂的第二类型的掺杂剂并且设置在所述半导体衬底上; 以及形成在半导体层中的图像传感器。

公开(公告)号：US07388187B1

公开(公告)日：2008-06-17

申请号：US11682428

申请日：2007-03-06

Applicant: Han-Chi Liu ,  Chung-Wei Chang ,  Shou-Gwo Wuu ,  Tong-Chern Ong ,  Chun-Yao Ko

Inventor： Han-Chi Liu ,  Chung-Wei Chang ,  Shou-Gwo Wuu ,  Tong-Chern Ong ,  Chun-Yao Ko

IPC: H01L31/00

CPC classification number: H01L27/14654 ,  H01L27/1463

Abstract: An image sensor device includes a semiconductor substrate having a first type of conductivity, a semiconductor layer having the first type of conductivity formed on the semiconductor substrate, and pixels formed in the semiconductor layer. The semiconductor layer includes a first deep well having the first type of conductivity and substantially underlying the plurality of pixels, and a second deep well having a second type of conductivity different from the first type of conductivity and substantially underlying the first deep well.

Abstract translation: 图像传感器装置包括具有第一导电类型的半导体衬底，在半导体衬底上形成具有第一类型导电性的半导体层和形成在半导体层中的像素。 半导体层包括具有第一类型导电性并且基本上位于多个像素下面的第一深阱，以及具有不同于第一类型导电性的第二类型导电性并且基本上位于第一深阱的第二深阱。

公开(公告)号：US08772854B2

公开(公告)日：2014-07-08

申请号：US13437503

申请日：2012-04-02

Applicant: Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

Inventor： Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

IPC: H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/0223 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/11517 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/66825

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract translation: 器件包括有源区和耦合电容。 电容器包括作为耦合电容器的上电容器板的第一浮置栅极和耦合电容器的下电容器板的掺杂半导体区域。 掺杂半导体区域包括在有源区的表面处的表面部分和比表面部分的底表面低的侧壁部分。 侧壁部分在有源区域的侧壁上。 电容器绝缘体设置在上电容器板和下电容器板之间。 电容绝缘体包括上部和比上部的底面低的侧壁部。

公开(公告)号：US08653623B2

公开(公告)日：2014-02-18

申请号：US13107409

申请日：2011-05-13

Applicant: Jyun-Ying Lin ,  Chun-Yao Ko ,  Ting-Chen Hsu

Inventor： Jyun-Ying Lin ,  Chun-Yao Ko ,  Ting-Chen Hsu

IPC: H01L23/52

CPC classification number: H01L21/76886 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract translation: 一次性可编程（OTP）器件包括至少一个与保险丝电耦合的晶体管。 保险丝包括在熔丝的第一节点和第二节点之间连续延伸的含硅线。 第一硅化物部分设置在含硅线上。 第二硅化物部分设置在含硅线上。 第二硅化物含有部分与第一硅化物含有部分分开预定距离。 预定距离基本上等于或小于含硅线的长度。

公开(公告)号：US08368130B2

公开(公告)日：2013-02-05

申请号：US12968047

申请日：2010-12-14

Applicant: Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

Inventor： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

IPC: H01L27/146 ,  H01L31/0232 ,  H01L31/0352

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

Abstract translation: 制造图像传感器的方法包括提供具有像素区域和逻辑区域的半导体衬底，在像素区域中形成光感测元件，以及在像素区域中形成第一晶体管和在逻辑区域中形成第二晶体管。 在逻辑区域中的像素区域和第二晶体管中形成第一晶体管的步骤包括在像素区域和逻辑区域中执行第一注入处理，在像素区域和逻辑区域中执行第二注入处理，以及执行 仅在逻辑区域中进行第三次植入过程。

公开(公告)号：US08133792B2

公开(公告)日：2012-03-13

申请号：US11309164

申请日：2006-07-04

Applicant: Victor-Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

Inventor： Victor-Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract translation: 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。

公开(公告)号：US20110133260A1

公开(公告)日：2011-06-09

申请号：US12968047

申请日：2010-12-14

Applicant: Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

Inventor： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

IPC: H01L31/113

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

Abstract translation: 制造图像传感器的方法包括提供具有像素区域和逻辑区域的半导体衬底，在像素区域中形成光感测元件，以及在像素区域中形成第一晶体管和在逻辑区域中形成第二晶体管。 在逻辑区域中的像素区域和第二晶体管中形成第一晶体管的步骤包括在像素区域和逻辑区域中执行第一注入处理，在像素区域和逻辑区域中执行第二注入处理，以及执行 仅在逻辑区域中进行第三次植入过程。

公开(公告)号：US08114752B2

公开(公告)日：2012-02-14

申请号：US12701521

申请日：2010-02-06

Applicant: Victor Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

Inventor： Victor Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract translation: 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。

公开(公告)号：US07879639B2

公开(公告)日：2011-02-01

申请号：US11735226

申请日：2007-04-13

Applicant: Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

Inventor： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

IPC: H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

Abstract translation: 制造图像传感器的方法包括提供具有像素区域和逻辑区域的半导体衬底，在像素区域中形成光感测元件，以及在像素区域中形成第一晶体管和在逻辑区域中形成第二晶体管。 在逻辑区域中的像素区域和第二晶体管中形成第一晶体管的步骤包括在像素区域和逻辑区域中执行第一注入处理，在像素区域和逻辑区域中执行第二注入处理，以及执行 仅在逻辑区域中进行第三次植入过程。

公开(公告)号：US20100140741A1

公开(公告)日：2010-06-10

申请号：US12701521

申请日：2010-02-06

Applicant: Victor Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

Inventor： Victor Chiang Liang ,  Chien-Kuo Yang ,  Hua-Chou Tseng ,  Chun-Yao Ko ,  Cheng-Wen Fan ,  Yu-Ho Chiang ,  Chih-Yuh Tzeng

IPC: H01L29/92

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract translation: 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。