公开(公告)号：US20130256772A1

公开(公告)日：2013-10-03

申请号：US13437503

申请日：2012-04-02

Applicant: Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

Inventor： Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/0223 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/11517 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/66825

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract translation: 器件包括有源区和耦合电容。 电容器包括作为耦合电容器的上电容器板的第一浮置栅极和耦合电容器的下电容器板的掺杂半导体区域。 掺杂半导体区域包括在有源区的表面处的表面部分和比表面部分的底表面低的侧壁部分。 侧壁部分在有源区域的侧壁上。 电容器绝缘体设置在上电容器板和下电容器板之间。 电容绝缘体包括上部和比上部的底面低的侧壁部。

公开(公告)号：US07485917B2

公开(公告)日：2009-02-03

申请号：US11390144

申请日：2006-03-28

Applicant: Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

Inventor： Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

IPC: H01L29/788

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/42328

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract translation: 公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。 电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。 盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。 电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。 此外，设置形成在第三绝缘层上的擦除栅极。

公开(公告)号：US20070093024A1

公开(公告)日：2007-04-26

申请号：US11390144

申请日：2006-03-28

Applicant: Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

Inventor： Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/42328

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract translation: 公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。 电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。 盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。 电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。 此外，设置形成在第三绝缘层上的擦除栅极。

公开(公告)号：US08772854B2

公开(公告)日：2014-07-08

申请号：US13437503

申请日：2012-04-02

Applicant: Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

Inventor： Ching-Hung Fu ,  Chun-Yao Ko ,  Tuo-Hsin Chien ,  Ting-Chen Hsu

IPC: H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/0223 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/76237 ,  H01L27/11517 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/66825

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract translation: 器件包括有源区和耦合电容。 电容器包括作为耦合电容器的上电容器板的第一浮置栅极和耦合电容器的下电容器板的掺杂半导体区域。 掺杂半导体区域包括在有源区的表面处的表面部分和比表面部分的底表面低的侧壁部分。 侧壁部分在有源区域的侧壁上。 电容器绝缘体设置在上电容器板和下电容器板之间。 电容绝缘体包括上部和比上部的底面低的侧壁部。

公开(公告)号：US20080305594A1

公开(公告)日：2008-12-11

申请号：US11828344

申请日：2007-07-25

Applicant: Chung-We Pan ,  Shou-Yu Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Shou-Yu Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers.

Abstract translation: 提供了一种用于制造非易失性存储器的方法。 平行布置的隔离结构设置在基板中并且从基板的表面突出以限定有源区。 与隔离结构相交的掩模层沉积在基板上。 掩模层的表面高于隔离结构的表面。 在衬底中形成掺杂区域。 绝缘层沉积在掩模层之间的衬底上。 绝缘层和掩模层具有不同的蚀刻选择性。 去除掩模层以露出基底。 在衬底上形成隧道介电层。 浮置栅极沉积在由隔离结构和绝缘层围绕的基板上。 浮动栅极的表面比隔离结构的表面低。 在衬底上沉积栅极间电介质层。 控制栅极设置在绝缘层之间。

公开(公告)号：US20080273390A1

公开(公告)日：2008-11-06

申请号：US11797613

申请日：2007-05-04

Applicant: Chung-We Pan ,  Henry Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Henry Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: G11C11/34 ,  H01L21/82

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114

Abstract: A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells. The aspect ratio of the gap between the cells is about 1.8 to 3.2. Many advantages are provided with such NAND flash memory fabricating by the self-aligned process of the present invention.

Abstract translation: 在本发明中公开了一种新颖的NAND闪存单元阵列及其制造方法。 NAND闪存单元阵列包括具有有源面积的衬底; 在所述有效区域上排列成行的多个单元; 覆盖所述电池的第一阻挡层和所述行的每个端部周围的有源区域; 沉积以填充细胞之间的间隙的第一氧化物; 沿着位于行的每个端部的电池的侧壁形成的氧化物间隔物; 以及形成在氧化物隔离物上的聚间隔物，其作为用于驱动该行电池的选择栅极。 细胞间隙的长宽比为1.8〜3.2。 通过本发明的自对准方法制造这种NAND闪速存储器提供了许多优点。

公开(公告)号：US20070272962A1

公开(公告)日：2007-11-29

申请号：US11465881

申请日：2006-08-21

Applicant: Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: H01L29/94 ,  H01L21/336 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract translation: 提供具有L形间隔物的半导体器件及其制造方法。 半导体器件包括衬底，复合间隔物和隧道绝缘层。 衬底包括浅沟槽隔离结构和相邻有源区。 复合间隔物形成在浅沟槽隔离结构的侧壁上，还包括第一绝缘层和L形第二绝缘层间隔物，其中第一绝缘层位于L形第二绝缘层间隔物和 基质。 隧道绝缘层位于有源区的衬底上，并与其相应侧上的复合衬垫的第一绝缘层相连。

公开(公告)号：US07524732B2

公开(公告)日：2009-04-28

申请号：US11465881

申请日：2006-08-21

Applicant: Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: H01L21/20

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract translation: 提供具有L形间隔物的半导体器件及其制造方法。 半导体器件包括衬底，复合间隔物和隧道绝缘层。 衬底包括浅沟槽隔离结构和相邻有源区。 复合间隔物形成在浅沟槽隔离结构的侧壁上，还包括第一绝缘层和L形第二绝缘层间隔物，其中第一绝缘层位于L形第二绝缘层间隔物和 基质。 隧道绝缘层位于有源区的衬底上，并与其相应侧上的复合衬垫的第一绝缘层相连。

公开(公告)号：US20090053870A1

公开(公告)日：2009-02-26

申请号：US12031653

申请日：2008-02-14

Applicant: CHUNG WE PAN ,  TZENG WEN TZENG ,  MING YU HO ,  YEN YU HSU ,  CHIH PING CHUNG ,  CHING HUNG FU

Inventor： CHUNG WE PAN ,  TZENG WEN TZENG ,  MING YU HO ,  YEN YU HSU ,  CHIH PING CHUNG ,  CHING HUNG FU

IPC: H01L21/8239

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/792

Abstract: A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate.

Abstract translation: 一种制备闪速存储器结构的方法包括以下步骤：在衬底上形成具有块侧壁的多个介质块，在介质块的块侧壁上形成多个第一间隔物，去除未覆盖的衬底的一部分 介质块和第一间隔物，以在衬底中形成多个沟槽，执行沉积工艺以形成填充沟槽的隔离电介质层，去除介质块以暴露第一间隔物的间隔壁侧壁，形成多个第二隔离物 所述第一间隔件的间隔件侧壁，以及去除未被所述第一间隔件，所述第二间隔件和所述隔离介电层覆盖的所述基板的一部分，以在所述基板中形成多个第二沟槽。