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    Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
    6.
    发明申请
    Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer 有权
    使用快速退火在SiGe层上形成均匀的Ni（Pt）Si（Ge）触点

    公开(公告)号：US20140054700A1

    公开(公告)日：2014-02-27

    申请号：US13611893

    申请日：2012-09-12

    申请人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    发明人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    IPC分类号： H01L27/12

    CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

    摘要翻译： 提供了不使用盖层形成光滑硅化物的技术。 一方面，提供一种FET器件。 FET器件包括在BOX上具有SOI层的SOI晶片和形成在晶片中的至少一个有源区域; 所述至少一个有效区域的一部分上的栅极堆叠，其用作所述装置的通道; 源极和漏极区域，其中该器件的源极和漏极区域包括选自硅和硅锗的半导体材料; 并且硅化物接触到器件的源极和漏极区域，其中在硅化物触点和半导体材料之间存在界面，并且其中界面的界面粗糙度小于约5纳米。

    Using fast anneal to form uniform Ni(Pt)Si(Ge) contacts on SiGe layer
    8.
    发明授权
    Using fast anneal to form uniform Ni(Pt)Si(Ge) contacts on SiGe layer 有权
    使用快速退火在SiGe层上形成均匀的Ni（Pt）Si（Ge）接触

    公开(公告)号：US08865556B2

    公开(公告)日：2014-10-21

    申请号：US13611893

    申请日：2012-09-12

    申请人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    发明人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/02

    CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

    摘要翻译： 提供了不使用盖层形成光滑硅化物的技术。 一方面，提供一种FET器件。 FET器件包括在BOX上具有SOI层的SOI晶片和形成在晶片中的至少一个有源区域; 所述至少一个有效区域的一部分上的栅极堆叠，其用作所述装置的通道; 源极和漏极区域，其中该器件的源极和漏极区域包括选自硅和硅锗的半导体材料; 并且硅化物接触到器件的源极和漏极区域，其中在硅化物触点和半导体材料之间存在界面，并且其中界面的界面粗糙度小于约5纳米。

    Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
    9.
    发明申请
    Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer 审中-公开
    使用快速退火在SiGe层上形成均匀的Ni（Pt）Si（Ge）触点

    公开(公告)号：US20140057399A1

    公开(公告)日：2014-02-27

    申请号：US13593725

    申请日：2012-08-24

    申请人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    发明人： Joseph S. Newbury ,  Kenneth Parker Rodbell ,  Zhen Zhang ,  Yu Zhu

    IPC分类号： H01L21/3205 ,  H01L21/336

    CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

    摘要翻译： 提供了不使用盖层形成光滑硅化物的技术。 一方面，提供了一种无帽层形成硅化物的方法。 该方法包括以下步骤。 提供了选自硅和硅锗的半导体材料。 在半导体材料上沉积至少一种硅化物金属。 半导体材料和至少一种硅化物金属在约400℃至约800℃的温度下退火，持续时间小于或等于约10毫秒，以形成硅化物。 还提供了FET器件和用于制造FET器件的方法。

    CROSSLINKED POLYMER BINDERS FOR ELECTROCHEMICAL ENERGY STORAGE DEVICES
    10.
    发明申请
    CROSSLINKED POLYMER BINDERS FOR ELECTROCHEMICAL ENERGY STORAGE DEVICES 审中-公开

    公开(公告)号：US20200350588A1

    公开(公告)日：2020-11-05

    申请号：US15780861

    申请日：2016-12-05

    申请人： Yu Zhu ,  Feng Zou

    发明人： Yu Zhu ,  Feng Zou

    IPC分类号： H01M4/62 ,  H01M4/139 ,  H01M10/0525

    摘要： An electrochemical storage device including a conductive material and an electrochemical storage device material held together by a covalently crosslinked binder matrix. A method of forming an electrode for an electrochemical storage device, the method including the steps of: mixing electrochemical storage device material, conductive material, linear polymer, and crosslinker with one or more solvents, the resultant mixture forming an electrode slurry, crosslinking the linear polymer with the crosslinker to thereby create a covalently crosslinked polymer network of the polymer and crosslinker, the crosslinked polymer network physically or chemically binding together the electrochemical storage device material and the conductive material.