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    Electronic-circuit assembling process
    1.
    发明授权
    Electronic-circuit assembling process 有权
    电子电路组装过程

    公开(公告)号：US09204586B2

    公开(公告)日：2015-12-01

    申请号：US13154837

    申请日：2011-06-07

    申请人： Daisuke Kato ,  Hiroyuki Haneda

    发明人： Daisuke Kato ,  Hiroyuki Haneda

    IPC分类号： H05K13/04 ,  H05K13/08

    CPC分类号： H05K13/0452 ,  H05K13/08 ,  H05K13/084 ,  H05K13/085 ,  Y10T29/49124

    摘要： An electronic-circuit assembling process to be carried out in an electronic-circuit assembling system, for assembling an electronic circuit, by mounting electronic circuit components supplied from a component supplier, onto a circuit board, wherein the electronic circuit components includes at least one of different-property components having respective different electrical properties. The process includes: (a) a different-property-component-related information obtaining step of obtaining a different-property-component-related information including (a-i) a property-related information that enables recognition of the electrical property of the different-property component supplied from the component supplier and (a-ii) a different-property-component supply position that is a position of the component supplier supplying the different-property component, such that the different-property-component-related information is obtained by detecting the property-related information and/or the different-property-component supply position; (b) a mounting step of mounting, based on information related to the different-property-component supply position, the electronic circuit components including the different-property component, onto the circuit board; and (c) a property-related information providing step of providing the circuit board with the property-related information of the different-property component mounted on the circuit board.

    摘要翻译： 一种在电子电路组装系统中进行的电子电路组装过程，用于组装电子电路，通过将从部件供应商提供的电子电路部件安装到电路板上，其中电子电路部件包括以下各项中的至少一个： 不同性质的组分具有不同的电性能。 该过程包括：（a）不同的属性组件相关信息获取步骤，用于获得不同的属性组件相关信息，所述信息包括（ai）能够识别不同属性的电性能的属性相关信息 从组件供应商提供的组件和（a-ii）作为供应不同属性组件的组件供应商的位置的不同的属性组件供应位置，使得通过检测不同的属性组件相关信息 财产相关信息和/或不同的财产成分供应位置; （b）基于与所述不同特性成分供给位置有关的信息，将包含所述不同特性成分的所述电子电路部件安装到所述电路基板上的安装步骤; （c）属性相关信息提供步骤，向电路板提供安装在电路板上的不同属性部件的属性相关信息。

    SHAPE MEASUREMENT METHOD AND SHAPE MEASUREMENT APPARATUS FOR TIRES
    4.
    发明申请
    SHAPE MEASUREMENT METHOD AND SHAPE MEASUREMENT APPARATUS FOR TIRES 有权
    形状测量方法和轮胎测量设备

    公开(公告)号：US20130002856A1

    公开(公告)日：2013-01-03

    申请号：US13635611

    申请日：2011-03-18

    申请人： Akinobu Mizutani ,  Daisuke Kato ,  Akira Togii ,  Kenichi Okude

    发明人： Akinobu Mizutani ,  Daisuke Kato ,  Akira Togii ,  Kenichi Okude

    IPC分类号： H04N7/18

    CPC分类号： G01B11/24 ,  G01B11/06 ,  G01B2210/52 ,  G01M17/027

    摘要： A shape measurement method for a tire includes: detecting an outer surface shape data and an inner surface shape of the tire from image data of the outer surface and the inner surface; subjecting irregularities along the tire circumferential direction around the tire in the outer surface shape data and in the inner surface shape data to Fourier transformation to take out primary waveform components respectively; adjusting the tire circumferential positions of both of the waveform components to adjust the tire circumferential positions thereof; adjusting the tire radial direction cross section positions of the outer surface shape data and the inner surface shape data from information about the placement angles and the positions of the first camera and the second camera; and synthesizing the outer surface shape data and the inner surface shape data based on the adjusted tire circumferential positions and the tire radial direction cross section positions.

    摘要翻译： 轮胎的形状测量方法包括：根据外表面和内表面的图像数据检测轮胎的外表面形状数据和内表面形状; 在外表面形状数据和内表面形状数据中沿着轮胎周向轮胎周围的不规则性分别进行傅立叶变换以分别取出主波形成分; 调整两个波形分量的轮胎周向位置，以调整其轮胎周向位置; 从关于第一相机和第二相机的位置角度和位置的信息调整外表面形状数据和内表面形状数据的轮胎径向横截面位置; 以及基于所调整的轮胎周向位置和轮胎径向横截面位置来合成外表面形状数据和内表面形状数据。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07414907B2

    公开(公告)日：2008-08-19

    申请号：US11766486

    申请日：2007-06-21

    申请人： Yasuyuki Kajitani ,  Daisuke Kato

    发明人： Yasuyuki Kajitani ,  Daisuke Kato

    IPC分类号： G11C7/02

    CPC分类号： G11C29/50008 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/10897

    摘要： A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs, a plurality of word lines connected to the memory cells, a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines, and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals. Two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.

    摘要翻译： 一种半导体存储器件，包括具有以矩阵形式布置的多个存储单元的存储单元阵列，在存储单元之间传送数据的多个位线对，包括多个读出放大器的读出放大器组， 包括多个读出放大器电路的读出放大器，并且多个读出放大器电路分别连接到多个位线对，以放大传送到位线对的数据，连接到存储器单元的多条字线， 分别对应于多个字线并且在多个字线上方布置的多个布线，以及多个针对每隔预定间隔将多条字线连接到多条布线的线迹部分。 在与感测放大器组中的每个针脚部分相对应的针脚区域的两侧分别形成读出放大器电路的两个有源区域彼此连接，并且在连接的有源区域上设置虚设晶体管。

    Navigation device
    8.
    发明授权
    Navigation device 有权
    导航设备

    公开(公告)号：US06662104B2

    公开(公告)日：2003-12-09

    申请号：US09736185

    申请日：2000-12-15

    申请人： Yasunobu Ito ,  Kunihiro Yamada ,  Daisuke Kato

    发明人： Yasunobu Ito ,  Kunihiro Yamada ,  Daisuke Kato

    IPC分类号： G01M1700

    CPC分类号： G01C21/26

    摘要： The navigation device of the invention includes a main processing unit provided with a CPU and storage means; a sub-processing unit connected to the main processing unit; connectors for connecting the main processing unit and the sub-processing unit; and functional components connected to the sub-processing unit. In this case, even when the specifications of the various functional component (s) connected to the sub-processing unit are different, by designing and manufacturing the sub-processing unit in conformance with each component, the main processing unit can be designed and manufactured as a general-purpose (standardized) product. Therefore, not only is the mountability of the navigation device improved, but also the cost thereof is reduced.

    摘要翻译： 本发明的导航装置包括具有CPU和存储装置的主处理单元; 连接到主处理单元的子处理单元; 用于连接主处理单元和子处理单元的连接器; 以及连接到子处理单元的功能组件。 在这种情况下，即使连接到子处理单元的各种功能部件的规格不同，通过根据各部件设计制造子处理单元，也可以对主处理单元进行设计制造 作为通用（标准化）产品。 因此，不仅可以提高导航装置的安装性，而且降低成本。

    Semiconductor memory device having redundancy system
    9.
    发明授权
    Semiconductor memory device having redundancy system 失效
    具有冗余系统的半导体存储器件

    公开(公告)号：US06646932B2

    公开(公告)日：2003-11-11

    申请号：US10162433

    申请日：2002-06-03

    申请人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

    发明人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/785

    摘要： A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

    摘要翻译： 半导体存储器件具有单元阵列，每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元，每个在单元阵列内被定义为一组存储单元，每个存储单元被布置 在所述单元阵列的第二方向上，每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元，用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件 用于替换电池阵列内的有缺陷的第二正常元件的元件。 在单元阵列第一/第二修复区域内被定义为具有第一/第二正常元素的组，并且允许由每个第一/第二冗余元素替换。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6021061A

    公开(公告)日：2000-02-01

    申请号：US208055

    申请日：1998-12-09

    申请人： Daisuke Kato ,  Yohji Watanabe

    发明人： Daisuke Kato ,  Yohji Watanabe

    IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C5/025

    摘要： At least one of the row- and column-selection mechanisms, including row- and column decoders, respectively, of a DRAM has a core circuit array and a control circuit array adjacent to each other. The core circuit array has an m-number of core circuit units which are substantially equivalent to each other, and each of which consists of an n-number of core circuits forming the decoders, respectively. The control circuit array has an m-number of control circuit units which are substantially equivalent to each other, and are connected to the core circuit units by interconnection wiring lines, respectively. The core circuit units and the control circuit units are arranged in a first direction with first and second pitches, respectively, which differ from each other. The second pitch is smaller than the first pitch, so that an additional region derived from the difference between the pitches is arranged along with the control circuit units in the first direction, and lead-out wiring lines from the core circuit array are arranged in the additional region.

    摘要翻译： 分别包括行和列选择机制的行和列选择机制中的至少一个包括具有彼此相邻的核心电路阵列和控制电路阵列。 核心电路阵列具有大量相互相等的m个核心电路单元，并且每个核心电路单元分别由形成解码器的n个核心电路组成。 控制电路阵列具有大量相互相等的m个控制电路单元，并且分别通过互连线路连接到核心电路单元。 核心电路单元和控制电路单元分别以彼此不同的第一和第二间距布置在第一方向上。 第二间距小于第一间距，使得从间距差导出的附加区域与控制电路单元一起布置在第一方向上，并且来自芯电路阵列的引出布线布置在 附加区域。