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    ELECTRICALLY-OPERATED MICROSCOPE
    2.
    发明申请
    ELECTRICALLY-OPERATED MICROSCOPE 审中-公开
    电动操作显微镜

    公开(公告)号：US20090073551A1

    公开(公告)日：2009-03-19

    申请号：US12184422

    申请日：2008-08-01

    申请人： Daisuke Kato

    发明人： Daisuke Kato

    IPC分类号： G02B21/00

    CPC分类号： G02B21/0016 ,  G02B21/0088 ,  G02B21/16 ,  G02B21/248 ,  G02B21/36

    摘要： The present invention provides an electrically-operated microscope including an arrangement switching unit, a driving unit, an operation inputting unit, and a control unit. The arrangement switching unit holds a plurality of optical elements and switches an arrangement of the plurality of optical elements. The driving unit drives the arrangement switching unit. The operation inputting unit inputs a predetermined single operation. The control unit controls the driving unit to control the arrangement of the plurality of optical elements, and performs a control of stopping a driving of the driving unit and enabling a manual revolution of the arrangement switching unit when the predetermined single operation is input by the operation inputting unit.

    摘要翻译： 本发明提供一种电动显微镜，其包括布置切换单元，驱动单元，操作输入单元和控制单元。 布置切换单元保持多个光学元件并切换多个光学元件的布置。 驱动单元驱动排列切换单元。 操作输入单元输入预定的单个操作。 控制单元控制驱动单元来控制多个光学元件的布置，并且当通过操作输入预定的单个操作时，执行停止驱动单元的驱动的控制并且能够进行布置切换单元的手动旋转 输入单元

    Semiconductor Memory Device
    3.
    发明申请
    Semiconductor Memory Device 失效
    半导体存储器件

    公开(公告)号：US20070258303A1

    公开(公告)日：2007-11-08

    申请号：US11766486

    申请日：2007-06-21

    申请人： Yasuyuki Kajitani ,  Daisuke Kato

    发明人： Yasuyuki Kajitani ,  Daisuke Kato

    IPC分类号： G11C7/02

    CPC分类号： G11C29/50008 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/10897

    摘要： A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs, a plurality of word lines connected to the memory cells, a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines, and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals. Two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.

    摘要翻译： 一种半导体存储器件，包括具有以矩阵形式布置的多个存储单元的存储单元阵列，在存储单元之间传送数据的多个位线对，包括多个读出放大器的读出放大器组， 包括多个读出放大器电路的读出放大器，并且多个读出放大器电路分别连接到多个位线对，以放大传送到位线对的数据，连接到存储器单元的多条字线， 分别对应于多个字线并且在多个字线上方布置的多个布线，以及多个针对每隔预定间隔将多条字线连接到多条布线的线迹部分。 在与感测放大器组中的每个针脚部分相对应的针脚区域的两侧分别形成读出放大器电路的两个有源区域彼此连接，并且在连接的有源区域上设置虚设晶体管。

    Position control mechanism
    4.
    发明申请
    Position control mechanism 审中-公开
    位置控制机制

    公开(公告)号：US20060201276A1

    公开(公告)日：2006-09-14

    申请号：US11360297

    申请日：2006-02-23

    申请人： Ken Nomura ,  Seiji Uno ,  Daisuke Kato

    发明人： Ken Nomura ,  Seiji Uno ,  Daisuke Kato

    IPC分类号： H02K41/02

    CPC分类号： B23Q1/44 ,  H02K41/03 ,  H02K2201/18 ,  Y10T74/20378

    摘要： A position control mechanism as here provided is capable of controlling the position of a control object in any of the fore-aft directions and the rotation directions without producing heat and dust. Air slides (S1, S2) are respectively mounted integrally with a pair of linear motors (M1, M2). First coupling members (6, 7) are respectively attached to the air slides and move integrally with them. Second coupling members (10, 11) are placed opposite each other and respectively attached to the first coupling members and allowed to rotate with respect to the first coupling members. Linear bearings (12, 13) are provided between the opposing sides of the second coupling members (10, 11). A pair of the second coupling members are relatively movable through the linear bearings. A moving body (14) is fixed to one of the pair of second coupling members.

    摘要翻译： 如此提供的位置控制机构能够控制控制对象在任何前后方向和旋转方向上的位置，而不产生热和灰尘。 空气滑块（S1，S2）分别与一对线性马达（M 1，M 2）一体地安装。 第一联接构件（6,7）分别附接到空气滑块并与它们一体移动。 第二联接构件（10,11）彼此相对放置并且分别附接到第一联接构件并允许相对于第一联接构件旋转。 直线轴承（12,13）设置在第二联接构件（10,11）的相对侧之间。 一对第二联接构件可通过直线轴承相对移动。 移动体（14）固定到一对第二联接构件中的一个。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07102947B2

    公开(公告)日：2006-09-05

    申请号：US11095883

    申请日：2005-04-01

    申请人： Yasuyuki Kajitani ,  Daisuke Kato

    发明人： Yasuyuki Kajitani ,  Daisuke Kato

    IPC分类号： G11C7/00 ,  G11C7/02

    CPC分类号： G11C29/50008 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/10897

    摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.

    摘要翻译： 一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对， 设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门， 在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路 多个可变电阻元件。

    Semiconductor memory device having redundancy system
    6.
    发明授权
    Semiconductor memory device having redundancy system 失效
    具有冗余系统的半导体存储器件

    公开(公告)号：US06834016B2

    公开(公告)日：2004-12-21

    申请号：US10421139

    申请日：2003-04-23

    申请人： Daisuke Kato ,  Yohji Watanabe

    发明人： Daisuke Kato ,  Yohji Watanabe

    IPC分类号： G11C700

    CPC分类号： G11C29/787

    摘要： A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

    摘要翻译： 一种具有存储器系统和冗余系统的半导体存储器件，包括用于修复存储器系统中的多个缺陷的冗余元件，包括多个地址熔丝组，每个地址熔丝组包括用于对存储器系统中的缺陷地址进行编程的地址熔丝，以及主器件 用于防止在不使用所述冗余元件时选择相应的冗余元件的熔丝，其中至少一个主熔丝由所述多个地址熔丝组中的至少两个熔丝组共享。

    MOS semiconductor device with memory cells each having storage capacitor and transfer transistor
    7.
    发明授权
    MOS semiconductor device with memory cells each having storage capacitor and transfer transistor 失效
    具有存储单元的MOS半导体器件各自具有存储电容器和转移晶体管

    公开(公告)号：US5638329A

    公开(公告)日：1997-06-10

    申请号：US420079

    申请日：1995-04-11

    申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

    发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

    IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

    摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. AMOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

    摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 AMOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。

    MOS semiconductor device with memory cells each having storage capacitor and transfer transistor
    8.
    发明授权
    MOS semiconductor device with memory cells each having storage capacitor and transfer transistor 失效
    具有存储单元的MOS半导体器件各自具有存储电容器和转移晶体管

    公开(公告)号：US5426604A

    公开(公告)日：1995-06-20

    申请号：US197409

    申请日：1994-02-16

    申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

    发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

    IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

    摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

    摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 MOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。