公开(公告)号：US06876588B2

公开(公告)日：2005-04-05

申请号：US10664464

申请日：2003-09-17

申请人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

发明人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

IPC分类号： G11C8/02 ,  G11C29/00 ,  G11C29/26 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/26 ,  G11C29/787 ,  G11C2029/2602

摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

公开(公告)号：US06646932B2

公开(公告)日：2003-11-11

申请号：US10162433

申请日：2002-06-03

申请人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

发明人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

摘要翻译： 半导体存储器件具有单元阵列，每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元，每个在单元阵列内被定义为一组存储单元，每个存储单元被布置 在所述单元阵列的第二方向上，每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元，用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件 用于替换电池阵列内的有缺陷的第二正常元件的元件。 在单元阵列第一/第二修复区域内被定义为具有第一/第二正常元素的组，并且允许由每个第一/第二冗余元素替换。

公开(公告)号：US20050122802A1

公开(公告)日：2005-06-09

申请号：US11040851

申请日：2005-01-20

申请人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

发明人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

IPC分类号： G11C8/02 ,  G11C29/00 ,  G11C29/26 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/26 ,  G11C29/787 ,  G11C2029/2602

摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

摘要翻译： 提供了一种半导体存储装置，其中只有一个缺陷元件被行冗余元件代替，以便在存储单元阵列中的多个元件是多个元件中的多个元件中的至少一个元件是有缺陷的情况下补偿缺陷 同时激活。 半导体存储装置包括阵列控制电路，其被配置为通过基于信号来防止接收到字线状态信号来中断故障元件的操作，以确定是否执行行冗余替换处理。 字线状态信号通过单个信号线输入到单元阵列单元中的多个存储块。

公开(公告)号：US06856561B2

公开(公告)日：2005-02-15

申请号：US10657790

申请日：2003-09-08

申请人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

发明人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.

摘要翻译： 半导体存储器件具有单元阵列，每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元，每个在单元阵列内被定义为一组存储单元，每个存储单元被布置 在所述单元阵列的第二方向上，每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元，用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件 用于替换电池阵列内的有缺陷的第二正常元件的元件。 在单元阵列第一/第二修复区域内被定义为具有允许由每个第一/第二冗余元件替换的第一/第二正常元素的组。

公开(公告)号：US07079432B2

公开(公告)日：2006-07-18

申请号：US11040851

申请日：2005-01-20

申请人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

发明人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

IPC分类号： G11C7/00

CPC分类号： G11C29/785 ,  G11C29/26 ,  G11C29/787 ,  G11C2029/2602

摘要： A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.

摘要翻译： 半导体存储装置具有通过单元晶体管同时激活连接到同一位线的多个字线的功能。 半导体存储装置包括基于行地址设置列冗余的修复区域的列冗余系统。 通过列冗余系统，当修复区域被设置为分割位线时，修复区域被设置为使得可以一起被激活的多个字线属于同一修复区域。

公开(公告)号：US6021061A

公开(公告)日：2000-02-01

申请号：US208055

申请日：1998-12-09

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C5/025

摘要： At least one of the row- and column-selection mechanisms, including row- and column decoders, respectively, of a DRAM has a core circuit array and a control circuit array adjacent to each other. The core circuit array has an m-number of core circuit units which are substantially equivalent to each other, and each of which consists of an n-number of core circuits forming the decoders, respectively. The control circuit array has an m-number of control circuit units which are substantially equivalent to each other, and are connected to the core circuit units by interconnection wiring lines, respectively. The core circuit units and the control circuit units are arranged in a first direction with first and second pitches, respectively, which differ from each other. The second pitch is smaller than the first pitch, so that an additional region derived from the difference between the pitches is arranged along with the control circuit units in the first direction, and lead-out wiring lines from the core circuit array are arranged in the additional region.

摘要翻译： 分别包括行和列选择机制的行和列选择机制中的至少一个包括具有彼此相邻的核心电路阵列和控制电路阵列。 核心电路阵列具有大量相互相等的m个核心电路单元，并且每个核心电路单元分别由形成解码器的n个核心电路组成。 控制电路阵列具有大量相互相等的m个控制电路单元，并且分别通过互连线路连接到核心电路单元。 核心电路单元和控制电路单元分别以彼此不同的第一和第二间距布置在第一方向上。 第二间距小于第一间距，使得从间距差导出的附加区域与控制电路单元一起布置在第一方向上，并且来自芯电路阵列的引出布线布置在 附加区域。

公开(公告)号：US06603689B2

公开(公告)日：2003-08-05

申请号：US10045780

申请日：2002-01-11

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/787

摘要： A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

公开(公告)号：US06373772B1

公开(公告)日：2002-04-16

申请号：US09886490

申请日：2001-06-22

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

摘要： A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.

公开(公告)号：US06343038B1

公开(公告)日：2002-01-29

申请号：US09653264

申请日：2000-08-31

申请人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

发明人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C29/14

摘要： In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

摘要翻译： 在包括位线预充电/均衡电路的半导体存储器件中，位线预充电/均衡电路的控制系统在正常工作模式和测试模式下改变。 在测试模式下，当内部激活信号变为非有效时，位线预充电/均衡电路暂时导通，然后位线预充电/均衡电路在配对位线的电位完全相等之后变为截止。

公开(公告)号：US06272061B1

公开(公告)日：2001-08-07

申请号：US09652158

申请日：2000-08-31

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C5/025 ,  G11C29/80

摘要： A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.

摘要翻译： 半导体集成电路器件具有半导体集成电路，其具有布置熔丝的第一布局部分，布置与保险丝对应的熔丝锁存电路的第二布局部分。 第一布局部分以熔丝区域中的第一重复间距布置，而第二布局部分以比熔丝锁存电路区域中的第一重复间距小的第二重复间距布置。 在由第一和第二重复间距之间的差异引起的空间中布置第三布局部分。 在第三布置部分中，在每个第二布局部分中的每一个中不可重复的图案中的至少一个和不需要在每个第二布局部分中重复的图案。