公开(公告)号：US08325532B2

公开(公告)日：2012-12-04

申请号：US12754149

申请日：2010-04-05

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C16/02 ,  G11C5/14 ,  G11C8/00 ,  G11C11/00

CPC分类号： G11C16/30 ,  G11C5/145

摘要： A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.

摘要翻译： 一种半导体集成电路装置，具备包括多个存储单元的多个平面的存储单元阵列，电源电压生成电路，具备：电压生成电路，其被配置为生成上述多个面共有的电源电压;选择部 数字检测电路，被配置为检测所述多个平面中的选定平面的数量;以及电阻可变电路，被配置为根据所选择的平面的数量来改变所述多个平面与所述电压产生电路之间的布线电阻 以及被配置为控制电源电压产生电路的控制电路。

公开(公告)号：US20080151640A1

公开(公告)日：2008-06-26

申请号：US11953319

申请日：2007-12-10

申请人： Eiichi MAKINO ,  Shigeo Ohshima

发明人： Eiichi MAKINO ,  Shigeo Ohshima

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1063 ,  G11C2207/105

摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

摘要翻译： 本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘 具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

公开(公告)号：US07219323B2

公开(公告)日：2007-05-15

申请号：US11107038

申请日：2005-04-15

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

摘要翻译： 用于布置平行导线以减小电容变化的系统和方法。 在一个实施例中，布置成线性阵列的多个第一部件通过对应的信号线耦合到该线性阵列的末端处的第二部件。 每个信号线具有垂直于线性阵列方向延伸的垂直部分，以及平行于线性阵列方向延伸的平行部分。 平行部分交错，使得更长的平行部分与较短的平行部分相邻，而不是简单地从最长到最短的布置。 在一个实施例中，平行部分的较长的一半在整个平行部分的长度上减小，而平行部分的较短的一半长度增加。 在另一个实施例中，连续更长/更短的平行部分是该系列的交替侧。

公开(公告)号：US06343038B1

公开(公告)日：2002-01-29

申请号：US09653264

申请日：2000-08-31

申请人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

发明人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C29/14

摘要： In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

摘要翻译： 在包括位线预充电/均衡电路的半导体存储器件中，位线预充电/均衡电路的控制系统在正常工作模式和测试模式下改变。 在测试模式下，当内部激活信号变为非有效时，位线预充电/均衡电路暂时导通，然后位线预充电/均衡电路在配对位线的电位完全相等之后变为截止。

公开(公告)号：US6045262A

公开(公告)日：2000-04-04

申请号：US44226

申请日：1998-03-19

申请人： Yoshikazu Igeta ,  Eiichi Makino ,  Mikio Mochitate ,  Hiroshi Abe ,  Takeshi Yano

发明人： Yoshikazu Igeta ,  Eiichi Makino ,  Mikio Mochitate ,  Hiroshi Abe ,  Takeshi Yano

IPC分类号： A61B5/055 ,  A61B6/04

CPC分类号： A61B6/0457 ,  A61B6/548

摘要： A control apparatus for controlling movement of a table supporting an object under inspection in a medical diagnosis system includes a driving power unit for moving the table, a position detector for outputting a signal indicating a position of the table, a positioning servo-control unit for controlling the driving power unit so that the detected position signal coincides with a given desired value, a manipulating force detector for outputting a force signal corresponding to a manipulating force applied by an operator, a force-to-position conversion unit for converting the force signal into a position change quantity for the table, a force control unit for controlling the driving power unit in accordance with the position change quantity so long as the manipulating force is being detected, and a change-over unit for selecting either the positioning servo-control unit or the force control unit in response to operation of the operator.

摘要翻译： 一种用于控制在医疗诊断系统中支撑检查对象的台的移动的控制装置，包括：用于移动工作台的驱动力单元，用于输出表示工作台位置的信号的位置检测器;定位伺服控制单元， 控制所述驱动功率单元，使得所检测的位置信号与给定的期望值一致;操作力检测器，用于输出对应于由操作者施加的操纵力的力信号;力到位置转换单元，用于将所述力信号 进入台的位置变化量;只要检测到操作力，根据位置变化量控制驱动力单元的力控制单元，以及用于选择定位伺服控制 单元或力控制单元响应于操作者的操作。

公开(公告)号：US5955891A

公开(公告)日：1999-09-21

申请号：US572381

申请日：1995-12-14

申请人： Eiichi Makino ,  Masaru Koyanagi

发明人： Eiichi Makino ,  Masaru Koyanagi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00361

摘要： The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

摘要翻译： 控制电压产生电路1输出的控制电压phi 1在外部电源电压Vcc低于晶体管P1的阈值的范围内处于低电平，但是当外部电源电压Vcc 上升。 在匹配外部电源电压Vcc之后，控制电压phi 1以与外部电源电压Vcc相同的方式增加。 通过使用具有如上所述的用于输出电路的特性的控制电压，受控的是低电压工作输出部分6的晶体管P4的栅极仅在低于预定值的电压下工作。 输出电路的全压工作输出部分5的晶体管P2总是基于数据输出控制电路3的控制信号phi H而工作。当外部电源电压低于预定值时，晶体管 P4完全打开，使其电导增加。 在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近的操作余量减小。

公开(公告)号：US5570047A

公开(公告)日：1996-10-29

申请号：US298837

申请日：1994-08-31

申请人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

发明人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

IPC分类号： G11C11/409 ,  G11C5/14 ,  H03K5/153 ,  G11C7/00

CPC分类号： G11C5/147

摘要： A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

摘要翻译： 半导体集成电路包括具有排列成矩阵的存储单元的存储单元块，每个位于与存储单元相邻的读出放大器，以及读出放大器控制电路，每个读出放大器控制电路位于存储单元块的外部。 读出放大器控制电路具有标准电压发生电路和用于接收标准电压并将驱动器信号传送到读出放大器以控制读出放大器的充电能力的控制电路。 源电压具有三个电压区域，第一，中间和第二区域。 在第一电压区域中，驱动信号的电位随源电压的增加而增加。 在中间电压区域（2.7〜3伏特）中，驱动信号的电位相对于源极电压的变化而变化，在第二电压区域中，驱动信号的电位随着源极电压的增加而减小 。

公开(公告)号：US20100271879A1

公开(公告)日：2010-10-28

申请号：US12754206

申请日：2010-04-05

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C16/04 ,  G11C5/14 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a common voltage generating circuit which maintains a fixed voltage supply capability, and a plurality of voltage generating circuits which are disposed in accordance with a number of the plurality of planes, and a control circuit configured to control the power supply voltage generating circuit.

摘要翻译： 半导体集成电路包括存储单元阵列，其包括多个平面，每个平面包括多个存储单元;电源电压产生电路，包括保持固定电压供应能力的公共电压发生电路;以及多个电压产生电路， 根据多个平面的数量设置，以及控制电路，其被配置为控制电源电压产生电路。

公开(公告)号：US07590027B2

公开(公告)日：2009-09-15

申请号：US11867443

申请日：2007-10-04

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G11C7/10

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays, a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays, a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal, and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal.

摘要翻译： 非易失性半导体器件包括多个字线，多个位线，多个存储单元阵列，具有连接到所述字线和所述位线的多个电可重新编程的存储器单元，数据程序控制部件，其编程 多个第一多位数据，每一个具有第一位数，或多个第二多位数据，每一个具有所述第一多位数据的第二位数的第二位数两倍于所述多个存储单元阵列; 存储从所述多个存储单元阵列中读取的每个所述字线的所述多个第一多位数据或所述多个第二多位数据的页缓冲器电路，传送所述多个第一多位数据 多位数据或所述多个第二多位数据，其从与所述第二时钟信号同步的所述页缓冲器电路中的每一个读取，具有周期wh 是第一时钟信号的两倍，以及从所述数据传送部分接收所述数据并与所述第一时钟信号同步地从外部输出所述数据的数据输出部分。

公开(公告)号：US20060236290A1

公开(公告)日：2006-10-19

申请号：US11107038

申请日：2005-04-15

申请人： Eiichi Makino

发明人： Eiichi Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

摘要翻译： 用于布置平行导线以减小电容变化的系统和方法。 在一个实施例中，布置成线性阵列的多个第一部件通过对应的信号线耦合到该线性阵列的末端处的第二部件。 每个信号线具有垂直于线性阵列方向延伸的垂直部分和平行于线性阵列方向延伸的平行部分。 平行部分交错，使得更长的平行部分与更短的平行部分相邻，而不是简单地从最长到最短的布置。 在一个实施例中，平行部分的较长的一半在整个平行部分的长度上减小，而平行部分的较短的一半长度增加。 在另一个实施例中，连续更长/更短的平行部分是该系列的交替侧。