公开(公告)号：US08014154B2

公开(公告)日：2011-09-06

申请号：US11766523

申请日：2007-06-21

申请人： Dae-Ho Lee

发明人： Dae-Ho Lee

IPC分类号： H05K1/00

CPC分类号： H05K1/0271 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09236 ,  H05K2201/09781 ,  Y10T29/49155 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In one embodiment, a circuit substrate comprises a substrate; and a warpage preventing pattern disposed on the substrate. The warpage preventing pattern comprises a first pattern at a first corner of the substrate and a second pattern at a second corner of the substrate. The first corner and the second corner are disposed adjacent to each other. An overall orientation of the first pattern is different from an overall orientation of the second pattern with respect to the substrate. The warping of a semiconductor package can be significantly reduced by cutting off stress lines in the corners of the circuit substrate. Various configurations and orientations of the warpage preventing pattern are provided in order to effectively block stress concentration in the corners of the circuit substrate.

摘要翻译： 在一个实施例中，电路基板包括基板; 以及设置在基板上的翘曲防止图案。 防翘曲图案包括在基板的第一角处的第一图案和在基板的第二拐角处的第二图案。 第一角和第二角彼此相邻设置。 第一图案的整体取向与第二图案相对于基板的整体取向不同。 通过切断电路基板的拐角处的应力线，可以显着降低半导体封装的翘曲。 提供防翘曲图案的各种构造和取向，以有效地阻止电路基板的角部的应力集中。

公开(公告)号：US20160190109A1

公开(公告)日：2016-06-30

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L25/16 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。

公开(公告)号：US20050158624A1

公开(公告)日：2005-07-21

申请号：US11025114

申请日：2004-12-30

申请人： Jin-Hwan Park ,  Tae-Byoung Oh ,  Dae-Ho Lee ,  Kil-Won Cho

发明人： Jin-Hwan Park ,  Tae-Byoung Oh ,  Dae-Ho Lee ,  Kil-Won Cho

IPC分类号： H01M4/13 ,  H01M4/133 ,  H01M4/134 ,  H01M4/136 ,  H01M4/36 ,  H01M4/38 ,  H01M4/48 ,  H01M4/58 ,  H01M4/587 ,  H01M4/62 ,  H01M6/16 ,  H01M10/05 ,  H01M10/0525 ,  H01M10/0566 ,  H01M10/058 ,  H01M10/0587 ,  H01M4/40

CPC分类号： H01M10/0525 ,  H01M4/0435 ,  H01M4/131 ,  H01M4/133 ,  H01M4/1393 ,  H01M4/525 ,  H01M4/587 ,  H01M4/621 ,  H01M4/622 ,  H01M10/0569 ,  H01M10/0583 ,  H01M10/0587 ,  H01M2004/027 ,  H01M2300/004 ,  Y02T10/7011

摘要： An anode for a lithium secondary battery contains an active material and a binder mixture. The active material can occlude or liberate lithium. The binder mixture includes a synthetic rubber-based latex-type binder, a cellulose-based thickener, and an acrylamide-based water-soluble polymer. The adhesive forces among electrode materials and between the electrode materials and a current collector are greatly increased. As a result, the number of battery defects, which are caused by low adhesive forces in the electrode plate manufacturing process, in particular, a rolling process, can be unexpectedly decreased. At the same time, high-rate discharge characteristics can be improved by decreasing the resistance at the interface between the electrode materials and the current collector.

摘要翻译： 锂二次电池的阳极含有活性物质和粘合剂混合物。 活性物质可以堵塞或释放锂。 粘合剂混合物包括合成橡胶基胶乳型粘合剂，纤维素基增稠剂和丙烯酰胺类水溶性聚合物。 电极材料之间以及电极材料和集电器之间的粘合力大大增加。 结果，电极板制造过程中的低粘合力，特别是轧制过程引起的电池缺陷的数量可能出人意料地减少。 同时，通过降低电极材料和集电体之间的界面处的电阻，可以提高高速放电特性。

公开(公告)号：US20110014402A1

公开(公告)日：2011-01-20

申请号：US12517917

申请日：2007-12-04

申请人： Ho-Yeul Choi ,  Ji-Sang Jeong ,  Dae-Ho Lee ,  Sang-Gil Lee ,  Hak-lae Lee ,  Chang-sun Han

发明人： Ho-Yeul Choi ,  Ji-Sang Jeong ,  Dae-Ho Lee ,  Sang-Gil Lee ,  Hak-lae Lee ,  Chang-sun Han

IPC分类号： B32B29/06 ,  C08F236/10 ,  C08F22/30 ,  C08F20/04 ,  C08F20/10 ,  C08L25/10 ,  C08L29/04

CPC分类号： B41M5/5254 ,  C08K3/36 ,  C08L9/08 ,  C08L25/14 ,  C08L29/04 ,  C08L53/02 ,  C08L2201/52 ,  C09D109/08 ,  C09D125/14 ,  C09D129/04 ,  C09D153/02

摘要： The present invention relates to a styrene-butadiene latex, a preparation method thereof and a coating liquid containing the same, more precisely a styrene-butadiene latex binder for ink-jet paper containing ethylenically unsaturated monomer by 0.1-1.5 weight parts with lowering surface negative charge density, a preparation method thereof and a coating liquid containing the same. The present invention provides a coating liquid for ink-jet paper having excellent price competitiveness and coating work-ability and at the same time reducing energy cost for drying process and thereby provides an ink-jet paper with excellent printing quality.

摘要翻译： 本发明涉及苯乙烯 - 丁二烯胶乳，其制备方法和含有该苯乙烯 - 丁二烯胶乳的涂布液，更准确地说，涉及含有0.1-1.5重量份的烯属不饱和单体的喷墨纸的苯乙烯 - 丁二烯胶乳粘合剂，具有降低的表面负 电荷密度，其制备方法和含有它们的涂布液。 本发明提供了具有优异的价格竞争力和涂布作业能力的喷墨纸用涂布液，同时降低了干燥工艺的能量成本，从而提供了具有优异印刷质量的喷墨纸。

公开(公告)号：US20080097019A1

公开(公告)日：2008-04-24

申请号：US11977157

申请日：2007-10-23

申请人： Dae-Ho Lee ,  Ji-Sang Jeong ,  Chang-Sun Han

发明人： Dae-Ho Lee ,  Ji-Sang Jeong ,  Chang-Sun Han

IPC分类号： C08L9/08 ,  C08K3/20 ,  C08K3/26 ,  C08L13/02

CPC分类号： C08F257/02 ,  C08F265/04 ,  C08F279/02 ,  C08L51/003 ,  C08L51/04 ,  C09D151/003 ,  C09D151/04 ,  D21H19/58 ,  C08L2666/02

摘要： Disclosed are paper coating latex, a method for preparing the same, and paper coating composition containing the same, characterized in that in the paper coating latex having a core-shell structure, the core is formed by the polymerization of monomer mixtures comprising 5 to 35 weight parts of ethylene unsaturated acid based on 100 weight parts of the core and the shell has glass transition temperature up to room temperature, lower than that of the core. The present invention has an effect of providing a high quality matte coated paper that has excellent printability such as ink drying rate, adhesion, etc., as well as low white paper gloss and improved print gloss by coating paper coating composition containing multi-layered paper coating latex having high swelling and contraction property on paper.

摘要翻译： 公开了纸涂布胶乳及其制备方法和含有该涂料组合物的纸涂料组合物，其特征在于在具有核 - 壳结构的纸涂布胶乳中，芯通过包含5至35的单体混合物的聚合形成 重量份的乙烯不饱和酸基于100重量份的核心和壳体的玻璃化转变温度高达室温，低于核心。 本发明的效果是通过涂布含有多层纸的纸涂料组合物，提供具有优异的可印刷性的高质量无光泽涂布纸，例如油墨干燥速度，粘合性等，以及低白皮书光泽度和改善的印刷光泽度 在纸上具有高膨胀和收缩性能的涂层胶乳。

公开(公告)号：US09466593B2

公开(公告)日：2016-10-11

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L23/02 ,  H01L25/16 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。

公开(公告)号：US08053045B2

公开(公告)日：2011-11-08

申请号：US12517917

申请日：2007-12-04

申请人： Ho-Yeul Choi ,  Ji-Sang Jeong ,  Dae-Ho Lee ,  Sang-Gil Lee ,  Hak-lae Lee ,  Chang-sun Han

发明人： Ho-Yeul Choi ,  Ji-Sang Jeong ,  Dae-Ho Lee ,  Sang-Gil Lee ,  Hak-lae Lee ,  Chang-sun Han

IPC分类号： B41M5/40

CPC分类号： B41M5/5254 ,  C08K3/36 ,  C08L9/08 ,  C08L25/14 ,  C08L29/04 ,  C08L53/02 ,  C08L2201/52 ,  C09D109/08 ,  C09D125/14 ,  C09D129/04 ,  C09D153/02

摘要： The present invention relates to a styrene-butadiene latex, a preparation method thereof and a coating liquid containing the same, more precisely a styrene-butadiene latex binder for ink-jet paper containing ethylenically unsaturated monomer by 0.1-1.5 weight parts with lowering surface negative charge density, a preparation method thereof and a coating liquid containing the same. The present invention provides a coating liquid for ink-jet paper having excellent price competitiveness and coating work-ability and at the same time reducing energy cost for drying process and thereby provides an ink-jet paper with excellent printing quality.

摘要翻译： 本发明涉及苯乙烯 - 丁二烯胶乳，其制备方法和含有该苯乙烯 - 丁二烯胶乳的涂布液，更准确地说，涉及含有0.1-1.5重量份的烯属不饱和单体的喷墨纸的苯乙烯 - 丁二烯胶乳粘合剂，具有降低的表面负 电荷密度，其制备方法和含有它们的涂布液。 本发明提供了具有优异的价格竞争力和涂布作业能力的喷墨纸用涂布液，同时降低了干燥工艺的能量成本，从而提供了具有优异印刷质量的喷墨纸。

公开(公告)号：US08728664B2

公开(公告)日：2014-05-20

申请号：US11025114

申请日：2004-12-30

申请人： Jin-Hwan Park ,  Tae-Byoung Oh ,  Dae-Ho Lee ,  Kil-Won Cho

发明人： Jin-Hwan Park ,  Tae-Byoung Oh ,  Dae-Ho Lee ,  Kil-Won Cho

IPC分类号： H01M4/13 ,  H01M4/58

CPC分类号： H01M10/0525 ,  H01M4/0435 ,  H01M4/131 ,  H01M4/133 ,  H01M4/1393 ,  H01M4/525 ,  H01M4/587 ,  H01M4/621 ,  H01M4/622 ,  H01M10/0569 ,  H01M10/0583 ,  H01M10/0587 ,  H01M2004/027 ,  H01M2300/004 ,  Y02T10/7011

摘要： An anode for a lithium secondary battery contains an active material and a binder mixture. The active material can occlude or liberate lithium. The binder mixture includes a synthetic rubber-based latex-type binder, a cellulose-based thickener, and an acrylamide-based water-soluble polymer. The adhesive forces among electrode materials and between the electrode materials and a current collector are greatly increased. As a result, the number of battery defects, which are caused by low adhesive forces in the electrode plate manufacturing process, in particular, a rolling process, can be unexpectedly decreased. At the same time, high-rate discharge characteristics can be improved by decreasing the resistance at the interface between the electrode materials and the current collector.

摘要翻译： 锂二次电池的阳极含有活性物质和粘合剂混合物。 活性物质可以堵塞或释放锂。 粘合剂混合物包括合成橡胶基胶乳型粘合剂，纤维素基增稠剂和丙烯酰胺类水溶性聚合物。 电极材料之间以及电极材料和集电器之间的粘合力大大增加。 结果，电极板制造过程中的低粘合力，特别是轧制过程引起的电池缺陷的数量可能出人意料地减少。 同时，通过降低电极材料和集电体之间的界面处的电阻，可以提高高速放电特性。

公开(公告)号：US08674000B2

公开(公告)日：2014-03-18

申请号：US11977157

申请日：2007-10-23

申请人： Dae-Ho Lee ,  Ji-Sang Jeong ,  Chang-Sun Han

发明人： Dae-Ho Lee ,  Ji-Sang Jeong ,  Chang-Sun Han

IPC分类号： C08L83/00 ,  C08L3/00

CPC分类号： C08F257/02 ,  C08F265/04 ,  C08F279/02 ,  C08L51/003 ,  C08L51/04 ,  C09D151/003 ,  C09D151/04 ,  D21H19/58 ,  C08L2666/02

摘要： Disclosed are paper coating latex, a method for preparing the same, and paper coating composition containing the same, characterized in that in the paper coating latex having a core-shell structure, the core is formed by the polymerization of monomer mixtures comprising 5 to 10 weight parts of ethylene unsaturated acid based on 100 weight parts of the core, wherein the amount of ethylene unsaturated acid in the shell is less than that in the core, and the shell has glass transition temperature up to room temperature, lower than that of the core. The present invention has an effect of providing a high quality matte coated paper that has excellent printability such as ink drying rate, adhesion, etc., as well as low white paper gloss and improved print gloss by coating paper coating composition containing multi-layered paper coating latex having high swelling and contraction property on paper.

摘要翻译： 公开了纸涂布胶乳及其制备方法，以及含有该涂料组合物的纸涂料组合物，其特征在于，在具有核 - 壳结构的纸涂布胶乳中，芯通过包含5至10个 重量份的基于100重量份芯的乙烯不饱和酸，其中壳中的乙烯不饱和酸的量小于芯中的乙烯不饱和酸的量，并且壳的玻璃化转变温度高达室温，低于 核心。 本发明的效果是通过涂布含有多层纸的纸涂料组合物，提供具有优异的可印刷性的高质量无光泽涂布纸，例如油墨干燥速度，粘合性等，以及低白皮书光泽度和改善的印刷光泽度 在纸上具有高膨胀和收缩性能的涂层胶乳。

公开(公告)号：US20060220257A1

公开(公告)日：2006-10-05

申请号：US11343617

申请日：2006-01-30

申请人： Dae-Ho Lee

发明人： Dae-Ho Lee

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip package includes a first chip group including at least one semiconductor chip on a substrate. The first chip group may be sealed to form a first package body. Connecting test terminals to ball pads allows package-level testing of the first chip group. A second chip group including at least one semiconductor chip may be provided on the first package body. The first package body and the second chip group may be sealed to form a second package body. The multi-chip package may further comprise an interposer substrate provided between the first package body and, for example, the lowest semiconductor chip of the second chip group. The interposer substrate may electrically connect the second chip group to the substrate.

摘要翻译： 多芯片封装包括在基板上包括至少一个半导体芯片的第一芯片组。 第一芯片组可以被密封以形成第一封装体。 将测试端子连接到球垫可以对第一个芯片组进行封装级测试。 包括至少一个半导体芯片的第二芯片组可以设置在第一封装主体上。 第一包装体和第二芯片组可以被密封以形成第二包装体。 多芯片封装还可以包括设置在第一封装体和例如第二芯片组的最低半导体芯片之间的插入器衬底。 插入器基板可以将第二芯片组电连接到基板。