公开(公告)号：US20230420523A1

公开(公告)日：2023-12-28

申请号：US18462595

申请日：2023-09-07

Applicant: DENSO CORPORATION

Inventor： Yusuke HAYAMA ,  Yusuke YAMASHITA ,  Keita KATAOKA ,  Yukihiko WATANABE

IPC: H01L29/32 ,  H01L29/16 ,  H01L29/06 ,  H01L29/861 ,  H01L29/78

CPC classification number: H01L29/32 ,  H01L29/1608 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/063

Abstract: A semiconductor device includes a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer includes a p-type semiconductor region disposed at a position exposed from the upper surface of the semiconductor layer and electrically connected to the second main electrode, and an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, and a hole trap is formed in the trap region.

公开(公告)号：US20190035882A1

公开(公告)日：2019-01-31

申请号：US16069914

申请日：2017-01-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04

Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.

公开(公告)号：US20170271457A1

公开(公告)日：2017-09-21

申请号：US15435833

申请日：2017-02-17

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Atsushi ONOGI ,  Toru ONISHI ,  Shuhei MITANI ,  Yusuke YAMASHITA ,  Katsuhiro KUTSUKI

IPC: H01L29/16 ,  H01L27/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/1608 ,  G01K7/01 ,  G01K7/015 ,  G01K7/028 ,  H01L23/34 ,  H01L27/0255 ,  H01L27/0716 ,  H01L27/2454 ,  H01L29/083 ,  H01L29/1095 ,  H01L29/6606 ,  H01L29/7397 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/12036

Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.

公开(公告)号：US20220278231A1

公开(公告)日：2022-09-01

申请号：US17747293

申请日：2022-05-18

Applicant: DENSO CORPORATION

Inventor： Jun SAITO ,  Youngshin EUM ,  Keita KATAOKA ,  Yusuke YAMASHITA ,  Yukihiko WATANABE ,  Katsuhiro KUTSUKI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423

Abstract: A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ε (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm−2), Q>ε*Ec/e.

公开(公告)号：US20220231164A1

公开(公告)日：2022-07-21

申请号：US17715381

申请日：2022-04-07

Applicant: DENSO CORPORATION

Inventor： Jun SAITO ,  Keita KATAOKA ,  Yusuke YAMASHITA ,  Yukihiko WATANABE ,  Katsuhiro KUTSUKI ,  Yasushi URAKAMI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

公开(公告)号：US20200043823A1

公开(公告)日：2020-02-06

申请号：US16487007

申请日：2018-01-26

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Tatsuji NAGAOKA ,  Yusuke YAMASHITA ,  Yasushi URAKAMI

IPC: H01L23/34 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/32 ,  H01L29/16

Abstract: A semiconductor device includes a semiconductor substrate comprising an upper surface and a lower surface, an upper electrode provided on the upper surface, and a lower electrode provided on the lower surface. The semiconductor substrate includes, in a planar view, a first section including a center of the semiconductor substrate and a second section located between the first section and a peripheral edge of the semiconductor substrate. The first and second sections each comprise a MOSFET structure including a body diode. The MOSFET structure in the first section and the MOSFET structure in the second section are different from each other such that a forward voltage drop of the body diode in the first section with respect to a current density is higher than a forward voltage drop of the body diode in the second section with respect to the current density.

公开(公告)号：US20190035883A1

公开(公告)日：2019-01-31

申请号：US16069927

申请日：2017-01-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04

Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate that includes a foundation layer; forming a deep trench in the foundation layer; and filling the deep trench with a deep layer having a second conductive type and a limiting layer having the first conductive type. In the filling the deep trench, growth of the deep layer from a bottom of the deep trench toward an opening inlet of the deep trench and growth of the limiting layer from a side face of the deep trench are achieved by: dominant epitaxial growth of a second conductive type layer over a first conductive type layer on the bottom of the deep trench; and dominant epitaxial growth of the first conductive type layer over the second conductive type layer on the side face of the deep trench, based on plane orientation dependency of the compound semiconductor during epitaxial growth.

公开(公告)号：US20190013392A1

公开(公告)日：2019-01-10

申请号：US16069622

申请日：2017-01-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/7813

Abstract: A method for manufacturing a compound semiconductor device includes causing epitaxial growth of a p-type impurity layer containing a compound semiconductor on a foundation layer containing the compound semiconductor. The causing the epitaxial growth includes performing pre-doping to preliminarily introduce dopant gas before introducing material gas for the epitaxial growth of the compound semiconductor. The dopant gas contains an organic metal material providing dopant of p-type impurities. An impurity concentration profile of the p-type impurity layer is controlled by controlling a time of the pre-doping.

公开(公告)号：US20200020814A1

公开(公告)日：2020-01-16

申请号：US16468059

申请日：2017-11-28

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hiroki MIYAKE ,  Yasushi URAKAMI ,  Yusuke YAMASHITA

IPC: H01L29/872 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.

公开(公告)号：US20220013666A1

公开(公告)日：2022-01-13

申请号：US17482840

申请日：2021-09-23

Applicant: DENSO CORPORATION

Inventor： Yasushi URAKAMI ,  Jun SAITO ,  Yusuke YAMASHITA

IPC: H01L29/78 ,  H01L29/10

Abstract: A semiconductor device includes a cell section having a plurality of gate structures, and an outer peripheral section surrounding the cell section. The cell section includes a semiconductor substrate, the plurality of gate structures, a first electrode and a second electrode. The cell section and the outer peripheral section includes a protective film made of a material having a thermal conductivity lower than that of the first electrode. The protective film extends from the outer peripheral section to an outer edge portion of the cell section adjacent to the outer peripheral section and covers a portion of the first electrode adjacent to the outer peripheral section.