公开(公告)号：US20170271457A1

公开(公告)日：2017-09-21

申请号：US15435833

申请日：2017-02-17

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Atsushi ONOGI ,  Toru ONISHI ,  Shuhei MITANI ,  Yusuke YAMASHITA ,  Katsuhiro KUTSUKI

IPC: H01L29/16 ,  H01L27/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/1608 ,  G01K7/01 ,  G01K7/015 ,  G01K7/028 ,  H01L23/34 ,  H01L27/0255 ,  H01L27/0716 ,  H01L27/2454 ,  H01L29/083 ,  H01L29/1095 ,  H01L29/6606 ,  H01L29/7397 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/12036

Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.

公开(公告)号：US20190386094A1

公开(公告)日：2019-12-19

申请号：US16304783

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Shuhei MITANI ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.

公开(公告)号：US20210151385A1

公开(公告)日：2021-05-20

申请号：US17159610

申请日：2021-01-27

Applicant: DENSO CORPORATION

Inventor： Aiko KAJI ,  Haruhito ICHIKAWA ,  Shuhei MITANI ,  Tomohiro MIMURA ,  Yukihiro WAKASUGI ,  Narumasa SOEJIMA

IPC: H01L23/544 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a surface of a semiconductor layer of a semiconductor substrate; forming a contact hole in the insulating film; forming a conductor material on the insulating film to be in contact with the semiconductor layer through the contact hole; and patterning the conductor material using an alignment key included in the conductor material.

公开(公告)号：US20210143070A1

公开(公告)日：2021-05-13

申请号：US17151821

申请日：2021-01-19

Applicant: DENSO CORPORATION

Inventor： Shinya TAKEI ,  Shuhei MITANI ,  Haruhito ICHIKAWA ,  Ippei TAKAHASHI ,  Yukihiro WAKASUGI

IPC: H01L21/66 ,  H01L21/02

Abstract: A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value α and an absolute value of a value β. A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value α. A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value β.

公开(公告)号：US20200161467A1

公开(公告)日：2020-05-21

申请号：US16729733

申请日：2019-12-30

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Shuhei MITANI ,  Yasuhiro EBIHARA ,  Yusuke YAMASHITA ,  Tadashi MISUMI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

公开(公告)号：US20200168732A1

公开(公告)日：2020-05-28

申请号：US16776821

申请日：2020-01-30

Applicant: DENSO CORPORATION

Inventor： Shuhei MITANI ,  Aiko KAJI ,  Yasuhiro EBIHARA ,  Tatsuji NAGAOKA ,  Sachiko AOI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.