公开(公告)号：US09000568B2

公开(公告)日：2015-04-07

申请号：US13244948

申请日：2011-09-26

Applicant: Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

Inventor： Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Abstract translation: 半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。 氧化物层位于衬底上。 金属氮氧化物层位于氧化物层上。 金属氧化物层位于金属氮氧化物层上。 此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

公开(公告)号：US08691688B2

公开(公告)日：2014-04-08

申请号：US13525568

申请日：2012-06-18

Applicant: Hsin-Yu Chen ,  Yu-Han Tsai ,  Chun-Ling Lin ,  Ching-Li Yang ,  Home-Been Cheng

Inventor： Hsin-Yu Chen ,  Yu-Han Tsai ,  Chun-Ling Lin ,  Ching-Li Yang ,  Home-Been Cheng

IPC: H01L21/44

CPC classification number: H01L21/76898

Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.

Abstract translation: 提供了一种处理衬底的方法。 该方法包括：提供衬底，其中衬底包括硅层; 蚀刻基板以形成空腔; 在腔的一部分中填充第一导体; 对所述第一导体执行第一热处理; 在腔中填充第二导体以填充空腔; 以及对所述第一导体和所述第二导体执行第二热处理。

公开(公告)号：US20130075874A1

公开(公告)日：2013-03-28

申请号：US13244948

申请日：2011-09-26

Applicant: Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

Inventor： Szu-Hao Lai ,  Yu-Ren Wang ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh ,  Te-Lin Sun

IPC: H01L29/06 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.

Abstract translation: 半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。 氧化物层位于衬底上。 金属氮氧化物层位于氧化物层上。 金属氧化物层位于金属氮氧化物层上。 此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

公开(公告)号：US07580194B2

公开(公告)日：2009-08-25

申请号：US11955291

申请日：2007-12-12

Applicant: Chun-Ling Lin

Inventor： Chun-Ling Lin

IPC: G02B9/00

CPC classification number: G02B15/177

Abstract: An exemplary projection lens includes, in this order from the screen-side thereof, a negative lens group having negative refraction of power, and a positive lens group having positive refraction of power. The positive and negative lens groups each include a number of positive and negative lenses. The focal length of the projection lens is adjustable. The projection lens satisfies the formulas of: −2 56, where F1, and F2 respectively represent the effective focal lengths of the negative lens group and the positive lens group, Fw is the shortest effective focal length of the projection lens, and Vg2 is the average of the Abbe numbers of the positive lenses in the positive lens group.

Abstract translation: 示例性的投影透镜从其屏幕侧依次包括具有负折射率的负透镜组和具有正的折射率的正透镜组。 正和负透镜组各自包括许多正和负透镜。 投影镜头的焦距可调。 投影透镜满足以下公式：-2 56，其中F1和F2分别表示负透镜组和正透镜组的有效焦距，Fw是投影透镜的最短有效焦距，Vg2是所述投影透镜的阿贝数的平均值 阳性透镜在正透镜组中。

公开(公告)号：US20130337645A1

公开(公告)日：2013-12-19

申请号：US13525568

申请日：2012-06-18

Applicant: Hsin-Yu Chen ,  Yu-Han Tsai ,  Chun-Ling Lin ,  Ching-Li Yang ,  Home-Been Cheng

Inventor： Hsin-Yu Chen ,  Yu-Han Tsai ,  Chun-Ling Lin ,  Ching-Li Yang ,  Home-Been Cheng

IPC: H01L21/768

CPC classification number: H01L21/76898

Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.

Abstract translation: 提供了一种处理衬底的方法。 该方法包括：提供衬底，其中衬底包括硅层; 蚀刻基板以形成空腔; 在腔的一部分中填充第一导体; 对所述第一导体执行第一热处理; 在腔中填充第二导体以填充空腔; 以及对所述第一导体和所述第二导体执行第二热处理。

公开(公告)号：US20130045594A1

公开(公告)日：2013-02-21

申请号：US13212187

申请日：2011-08-18

Applicant: Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

Inventor： Yu-Ren Wang ,  Te-Lin Sun ,  Szu-Hao Lai ,  Po-Chun Chen ,  Chih-Hsun Lin ,  Che-Nan Tsai ,  Chun-Ling Lin ,  Chiu-Hsien Yeh

IPC: H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及 对第一功函数金属层进行解耦等离子体氧化。

公开(公告)号：US20120305403A1

公开(公告)日：2012-12-06

申请号：US13154420

申请日：2011-06-06

Applicant: Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Meng-Hong Tsai

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Meng-Hong Tsai

IPC: C25D7/12 ,  C25D5/00

CPC classification number: C25D5/54 ,  C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76879

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract translation: 提供电化学镀工艺。 半导体结构设置在电镀平台中。 进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。 在预电镀步骤之后，对半导体结构进行第一电镀步骤。

公开(公告)号：US07564634B2

公开(公告)日：2009-07-21

申请号：US11946325

申请日：2007-11-28

Applicant: Chun-Ling Lin ,  Chun-Hsiang Huang ,  Chung Lee

Inventor： Chun-Ling Lin ,  Chun-Hsiang Huang ,  Chung Lee

IPC: G02B9/62 ,  G02B13/04

CPC classification number: G02B9/62 ,  G02B13/005 ,  G02B13/22

Abstract: A lens system comprises a first lens negative in power, a second lens positive in power, a third lens negative in power, a fourth lens positive in power, a fifth lens negative in power, and a sixth lens positive in power. The lens system meets a criteria of TT/f≦1.68 and 0.3

Abstract translation: 透镜系统包括：功率为负的第一透镜，功率正的第二透镜，功率为负的第三透镜，功率为正的第四透镜，功率为负的第五透镜，以及功率为正的第六透镜。 透镜系统满足TT / f <= 1.68和0.3

公开(公告)号：US20130320537A1

公开(公告)日：2013-12-05

申请号：US13483074

申请日：2012-05-30

Applicant: Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US08481425B2

公开(公告)日：2013-07-09

申请号：US13108969

申请日：2011-05-16

Applicant: Yen-Liang Lu ,  Chun-Ling Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Meng-Hong Tsai

Inventor： Yen-Liang Lu ,  Chun-Ling Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Meng-Hong Tsai

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L21/76828 ,  H01L21/76831

Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.

Abstract translation: 公开了一种制造硅通孔结构的方法。 该方法包括以下步骤：提供半导体衬底; 在半导体衬底中形成穿硅通孔; 覆盖穿通硅通孔内的衬垫; 在衬垫上进行烘烤过程; 在衬垫上形成阻挡层; 以及在所述贯通硅通孔中形成贯通硅通孔电极。